Max Filippov 2c09eee112 target-xtensa: add basic tests for cache opcodes ... Test that non-locking prefetch operations don't cause exceptions on missing TLB and that other 'hit' cache operations do. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>		2014-02-24 04:47:02 +04:00
..
alpha
cris
lm32	tests: lm32: new rule for single test cases	2014-02-04 19:34:29 +01:00
mips	target-mips: correct the values in the DSP tests	2013-07-30 17:48:24 +02:00
openrisc	target-openrisc: Correct carry flag check of l.addc and l.addic test cases	2013-11-20 21:47:46 +08:00
xtensa	target-xtensa: add basic tests for cache opcodes	2014-02-24 04:47:02 +04:00
hello-arm.c
hello-i386.c
hello-mips.c
linux-test.c	remove some double-includes	2013-05-18 16:35:12 +04:00
Makefile
pi_10.com
runcom.c
sha1.c
test_path.c
test-arm-iwmmxt.s
test-i386-code16.S
test-i386-fprem.c
test-i386-muldiv.h
test-i386-shift.h
test-i386-ssse3.c
test-i386-vm86.S
test-i386.c
test-i386.h
test-mmap.c
testthread.c