qemu-e2k/target/ppc
Daniel Henrique Barboza 1f26c75191 PPC64/TCG: Implement 'rfebb' instruction
An Event-Based Branch (EBB) allows applications to change the NIA when a
event-based exception occurs. Event-based exceptions are enabled by
setting the Branch Event Status and Control Register (BESCR). If the
event-based exception is enabled when the exception occurs, an EBB
happens.

The following operations happens during an EBB:

- Global Enable (GE) bit of BESCR is set to 0;
- bits 0-61 of the Event-Based Branch Return Register (EBBRR) are set
to the the effective address of the NIA that would have executed if the EBB
didn't happen;
- Instruction fetch and execution will continue in the effective address
contained in the Event-Based Branch Handler Register (EBBHR).

The EBB Handler will process the event and then execute the Return From
Event-Based Branch (rfebb) instruction. rfebb sets BESCR_GE and then
redirects execution to the address pointed in EBBRR. This process is
described in the PowerISA v3.1, Book II, Chapter 6 [1].

This patch implements the rfebb instruction. Descriptions of all
relevant BESCR bits are also added - this patch is only using BESCR_GE,
but the next patches will use the remaining bits.

[1] https://wiki.raptorcs.com/w/images/f/f5/PowerISA_public.v3.1.pdf

Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-9-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17 17:57:19 +01:00
..
translate PPC64/TCG: Implement 'rfebb' instruction 2021-12-17 17:57:19 +01:00
arch_dump.c target/ppc: Introduce ppc_interrupts_little_endian() 2021-07-09 10:38:18 +10:00
compat.c powerpc tcg: Fix Lesser GPL version number 2020-11-15 16:38:50 +01:00
cpu_init.c target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event 2021-12-17 17:57:18 +01:00
cpu-models.c target/ppc: remove 401/403 CPUs 2021-12-17 17:57:16 +01:00
cpu-models.h target/ppc: remove 401/403 CPUs 2021-12-17 17:57:16 +01:00
cpu-param.h
cpu-qom.h target/ppc: remove 401/403 CPUs 2021-12-17 17:57:16 +01:00
cpu.c target/ppc: ppc_store_fpscr doesn't update bits 0 to 28 and 52 2021-12-17 17:57:13 +01:00
cpu.h PPC64/TCG: Implement 'rfebb' instruction 2021-12-17 17:57:19 +01:00
dfp_helper.c target/ppc: Move ddedpd[q],denbcd[q],dscli[q],dscri[q] to decodetree 2021-11-09 10:32:52 +11:00
excp_helper.c PPC64/TCG: Implement 'rfebb' instruction 2021-12-17 17:57:19 +01:00
fpu_helper.c target/ppc: move xscvqpdp to decodetree 2021-12-17 17:57:18 +01:00
gdbstub.c target/ppc: Fix XER access in gdbstub 2021-10-21 11:42:47 +11:00
helper_regs.c target/ppc: enable PMU instruction count 2021-12-17 17:57:18 +01:00
helper_regs.h target/ppc: Remove env->immu_idx and env->dmmu_idx 2021-05-04 11:41:25 +10:00
helper.h PPC64/TCG: Implement 'rfebb' instruction 2021-12-17 17:57:19 +01:00
insn32.decode PPC64/TCG: Implement 'rfebb' instruction 2021-12-17 17:57:19 +01:00
insn64.decode target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd instructions 2021-11-09 10:32:53 +11:00
int_helper.c target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd instructions 2021-11-09 10:32:53 +11:00
internal.h target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemu 2021-11-02 07:00:52 -04:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
kvm_ppc.h target/ppc: Support for H_RPT_INVALIDATE hcall 2021-07-09 11:01:06 +10:00
kvm-stub.c
kvm.c target/ppc: Support for H_RPT_INVALIDATE hcall 2021-07-09 11:01:06 +10:00
machine.c target/ppc: updated vscr manipulation in machine.c 2021-05-19 10:30:28 +10:00
mem_helper.c accel/tcg: Move cpu_atomic decls to exec/cpu_ldst.h 2021-10-13 08:14:54 -07:00
meson.build target/ppc: introduce PMUEventType and PMU overflow timers 2021-12-17 17:57:18 +01:00
mfrom_table_gen.c
mfrom_table.c.inc meson: rename included C source files to .c.inc 2020-08-21 06:18:30 -04:00
misc_helper.c target/ppc: fold ppc_store_ptcr into it's only caller 2021-06-03 13:22:06 +10:00
mmu_common.c target/ppc: remove 401/403 CPUs 2021-12-17 17:57:16 +01:00
mmu_helper.c target/ppc: remove 401/403 CPUs 2021-12-17 17:57:16 +01:00
mmu-book3s-v3.c target/ppc: Introduce ppc_xlate 2021-07-09 10:38:19 +10:00
mmu-book3s-v3.h target/ppc: introduce mmu-books.h 2021-07-09 10:38:19 +10:00
mmu-books.h target/ppc: introduce mmu-books.h 2021-07-09 10:38:19 +10:00
mmu-hash32.c target/ppc: change ppc_hash32_xlate to use mmu_idx 2021-07-09 10:38:19 +10:00
mmu-hash32.h target/ppc: change ppc_hash32_xlate to use mmu_idx 2021-07-09 10:38:19 +10:00
mmu-hash64.c target/ppc: fix Hash64 MMU update of PTE bit R 2021-11-29 21:00:08 +01:00
mmu-hash64.h target/ppc: fix Hash64 MMU update of PTE bit R 2021-11-29 21:00:08 +01:00
mmu-radix64.c target/ppc: fix address translation bug for radix mmus 2021-07-09 10:38:19 +10:00
mmu-radix64.h target/ppc: fix address translation bug for radix mmus 2021-07-09 10:38:19 +10:00
monitor.c target/ppc: Fix XER access in monitor 2021-10-21 11:42:47 +11:00
power8-pmu-regs.c.inc target/ppc: enable PMU instruction count 2021-12-17 17:57:18 +01:00
power8-pmu.c target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event 2021-12-17 17:57:18 +01:00
power8-pmu.h target/ppc: enable PMU instruction count 2021-12-17 17:57:18 +01:00
spr_tcg.h target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event 2021-12-17 17:57:18 +01:00
tcg-stub.c target/ppc: created tcg-stub.c file 2021-06-03 13:22:06 +10:00
timebase_helper.c powerpc tcg: Fix Lesser GPL version number 2020-11-15 16:38:50 +01:00
trace-events target/ppc: Convert debug to trace events (exceptions) 2021-09-30 12:26:06 +10:00
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
translate.c PPC64/TCG: Implement 'rfebb' instruction 2021-12-17 17:57:19 +01:00
user_only_helper.c target/ppc: Implement ppc_cpu_record_sigsegv 2021-11-02 07:00:52 -04:00