OpenE2K/qemu-e2k
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qemu-e2k/target/riscv
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Bin Meng c9711bd778 target/riscv: cpu: Enable native debug feature 
Turn on native debug feature by default for all CPUs.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220421003324.1134983-6-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-22 10:35:16 +10:00
..
insn_trans
target/riscv: optimize helper for vmv<nr>r.v
2022-04-22 10:35:16 +10:00
arch_dump.c
…
bitmanip_helper.c
target/riscv: Add rev8 instruction, removing grev/grevi
2021-10-07 08:41:33 +10:00
cpu_bits.h
target/riscv: Add *envcfg* CSRs support
2022-04-22 10:35:16 +10:00
cpu_helper.c
hw/intc: Make RISC-V ACLINT mtime MMIO register writable
2022-04-22 10:35:16 +10:00
cpu_user.h
…
cpu-param.h
…
cpu.c
target/riscv: cpu: Enable native debug feature
2022-04-22 10:35:16 +10:00
cpu.h
target/riscv: cpu: Add a config option for native debug
2022-04-22 10:35:16 +10:00
csr.c
target/riscv: csr: Hook debug CSR read/write
2022-04-22 10:35:16 +10:00
debug.c
target/riscv: csr: Hook debug CSR read/write
2022-04-22 10:35:16 +10:00
debug.h
target/riscv: csr: Hook debug CSR read/write
2022-04-22 10:35:16 +10:00
fpu_helper.c
target/riscv: add support for zhinx/zhinxmin
2022-03-03 13:14:50 +10:00
gdbstub.c
target/riscv: correct "code should not be reached" for x-rv128
2022-02-16 12:24:18 +10:00
helper.h
target/riscv: optimize helper for vmv<nr>r.v
2022-04-22 10:35:16 +10:00
insn16.decode
target/riscv: accessors to registers upper part and 128-bit load/store
2022-01-08 15:46:10 +10:00
insn32.decode
target/riscv: add support for svinval extension
2022-02-16 12:25:52 +10:00
instmap.h
…
internals.h
target/riscv: add support for zhinx/zhinxmin
2022-03-03 13:14:50 +10:00
Kconfig
meson: Introduce target-specific Kconfig
2021-07-09 18:21:34 +02:00
kvm_riscv.h
target/riscv: Support setting external interrupt by KVM
2022-01-21 15:52:56 +10:00
kvm-stub.c
target/riscv: Support setting external interrupt by KVM
2022-01-21 15:52:56 +10:00
kvm.c
Remove qemu-common.h include from most units
2022-04-06 14:31:55 +02:00
m128_helper.c
target/riscv: support for 128-bit M extension
2022-01-08 15:46:10 +10:00
machine.c
target/riscv: machine: Add debug state description
2022-04-22 10:35:16 +10:00
meson.build
target/riscv: Add initial support for the Sdtrig extension
2022-04-22 10:35:16 +10:00
monitor.c
target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
2021-10-22 07:47:51 +10:00
op_helper.c
compiler.h: replace QEMU_NORETURN with G_NORETURN
2022-04-21 17:03:51 +04:00
pmp.c
target/riscv/pmp: fix NAPOT range computation overflow
2022-04-22 10:35:16 +10:00
pmp.h
target: Include missing 'cpu.h'
2022-03-06 13:15:42 +01:00
sbi_ecall_interface.h
target/riscv: Handle KVM_EXIT_RISCV_SBI exit
2022-01-21 15:52:56 +10:00
trace-events
…
trace.h
…
translate.c
exec/translator: Pass the locked filepointer to disas_log hook
2022-04-20 10:51:11 -07:00
vector_helper.c
target/riscv: fix start byte for vmv<nf>r.v when vstart != 0
2022-04-22 10:35:16 +10:00
XVentanaCondOps.decode
target/riscv: Add XVentanaCondOps custom extension
2022-02-16 12:24:18 +10:00