Frank Chang 235d1161d4 target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns ... Vector widening conversion instructions are provided to and from all supported integer EEWs for Zve64f extension. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220118014522.13613-9-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2022-01-21 15:52:56 +10:00
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insn_trans	target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns	2022-01-21 15:52:56 +10:00
arch_dump.c
bitmanip_helper.c
cpu_bits.h	target/riscv: actual functions to realize crs 128-bit insns	2022-01-08 15:46:10 +10:00
cpu_helper.c	target/riscv: rvv-1.0: Add Zve64f extension into RISC-V	2022-01-21 15:52:56 +10:00
cpu_user.h
cpu-param.h
cpu.c	target/riscv: rvv-1.0: Add Zve64f extension into RISC-V	2022-01-21 15:52:56 +10:00
cpu.h	target/riscv: rvv-1.0: Add Zve64f extension into RISC-V	2022-01-21 15:52:56 +10:00
csr.c	target/riscv: rvv-1.0: Add Zve64f extension into RISC-V	2022-01-21 15:52:56 +10:00
fpu_helper.c	target/riscv: add "set round to odd" rounding mode helper function	2021-12-20 14:53:31 +10:00
gdbstub.c	target/riscv: setup everything for rv64 to support rv128 execution	2022-01-08 15:46:10 +10:00
helper.h	target/riscv: helper functions to wrap calls to 128-bit csr insns	2022-01-08 15:46:10 +10:00
insn16.decode	target/riscv: accessors to registers upper part and 128-bit load/store	2022-01-08 15:46:10 +10:00
insn32.decode	target/riscv: support for 128-bit M extension	2022-01-08 15:46:10 +10:00
instmap.h
internals.h	target/riscv: add "set round to odd" rounding mode helper function	2021-12-20 14:53:31 +10:00
Kconfig
kvm_riscv.h	target/riscv: Support setting external interrupt by KVM	2022-01-21 15:52:56 +10:00
kvm-stub.c	target/riscv: Support setting external interrupt by KVM	2022-01-21 15:52:56 +10:00
kvm.c	target/riscv: Implement virtual time adjusting with vm state changing	2022-01-21 15:52:56 +10:00
m128_helper.c	target/riscv: support for 128-bit M extension	2022-01-08 15:46:10 +10:00
machine.c	target/riscv: Support virtual time context synchronization	2022-01-21 15:52:56 +10:00
meson.build	target/riscv: Support start kernel directly by KVM	2022-01-21 15:52:56 +10:00
monitor.c
op_helper.c	target/riscv: helper functions to wrap calls to 128-bit csr insns	2022-01-08 15:46:10 +10:00
pmp.c
pmp.h
sbi_ecall_interface.h	target/riscv: Handle KVM_EXIT_RISCV_SBI exit	2022-01-21 15:52:56 +10:00
trace-events
trace.h
translate.c	target/riscv: rvv-1.0: Add Zve64f extension into RISC-V	2022-01-21 15:52:56 +10:00
vector_helper.c	target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm	2021-12-20 14:53:31 +10:00