Philippe Mathieu-Daudé 491b3cca36 target/ppc: Use tcg_constant_i64() in gen_brh() ... The mask of the Byte-Reverse Halfword opcode is a read-only constant. We can avoid using a TCG temporary by moving the mask to the constant pool. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211003141711.3673181-3-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>		2021-10-21 11:42:47 +11:00
..
alpha	target/alpha: Drop checks for singlestep_enabled	2021-10-15 16:39:14 -07:00
arm	target/arm: Drop checks for singlestep_enabled	2021-10-15 16:39:14 -07:00
avr	target/avr: Drop checks for singlestep_enabled	2021-10-15 16:39:14 -07:00
cris	target/cris: Drop checks for singlestep_enabled	2021-10-15 16:39:14 -07:00
hexagon	target/hexagon: Drop checks for singlestep_enabled	2021-10-15 16:39:14 -07:00
hppa	target/hppa: Drop checks for singlestep_enabled	2021-10-15 16:39:14 -07:00
i386	target/i386: Drop check for singlestep_enabled	2021-10-15 16:39:14 -07:00
m68k	target/m68k: Drop checks for singlestep_enabled	2021-10-15 16:39:14 -07:00
microblaze	target/microblaze: Drop checks for singlestep_enabled	2021-10-15 16:39:14 -07:00
mips	target/mips: Remove unused TCG temporary in gen_mipsdsp_accinsn()	2021-10-18 00:41:36 +02:00
nios2
openrisc	target/openrisc: Drop checks for singlestep_enabled	2021-10-15 16:39:14 -07:00
ppc	target/ppc: Use tcg_constant_i64() in gen_brh()	2021-10-21 11:42:47 +11:00
riscv	target/riscv: Remove exit_tb and lookup_and_goto_ptr	2021-10-15 16:39:14 -07:00
rx	target/rx: Drop checks for singlestep_enabled	2021-10-15 16:39:14 -07:00
s390x	target/s390x: Drop check for singlestep_enabled	2021-10-15 16:39:14 -07:00
sh4	target/sh4: Drop check for singlestep_enabled	2021-10-15 16:39:14 -07:00
sparc
tricore	target/tricore: Drop check for singlestep_enabled	2021-10-15 16:39:14 -07:00
xtensa	target/xtensa: Drop check for singlestep_enabled	2021-10-15 16:39:15 -07:00
Kconfig
meson.build