qemu-e2k/target-lm32
Andreas Färber 259186a7d2 cpu: Move halted and interrupt_request fields to CPUState
Both fields are used in VMState, thus need to be moved together.
Explicitly zero them on reset since they were located before
breakpoints.

Pass PowerPCCPU to kvmppc_handle_halt().

Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-03-12 10:35:55 +01:00
..
Makefile.objs target-lm32: switch to AREG0 free mode 2012-09-15 17:44:32 +00:00
README lm32: todo and documentation 2011-03-07 13:42:37 +01:00
TODO lm32: todo and documentation 2011-03-07 13:42:37 +01:00
cpu-qom.h cpu: Introduce ENV_OFFSET macros 2013-03-03 14:28:28 +00:00
cpu.c cpu: Add CPUArchState pointer to CPUState 2013-02-16 14:51:00 +01:00
cpu.h cpu: Move halted and interrupt_request fields to CPUState 2013-03-12 10:35:55 +01:00
helper.c target-lm32: Move TCG initialization to LM32CPU initfn 2013-02-16 14:50:58 +01:00
helper.h exec: move include files to include/exec/ 2012-12-19 08:31:31 +01:00
machine.c target-lm32: Don't overuse CPUState 2012-03-14 22:20:25 +01:00
op_helper.c cpu: Move halted and interrupt_request fields to CPUState 2013-03-12 10:35:55 +01:00
translate.c gen-icount.h: Rename gen_icount_start/end to gen_tb_start/end 2013-03-03 14:29:08 +00:00

README

LatticeMico32 target
--------------------

General
-------
All opcodes including the JUART CSRs are supported.


JTAG UART
---------
JTAG UART is routed to a serial console device. For the current boards it
is the second one. Ie to enable it in the qemu virtual console window use
the following command line parameters:
  -serial vc -serial vc
This will make serial0 (the lm32_uart) and serial1 (the JTAG UART)
available as virtual consoles.


Programmatically terminate the emulator
----------------------------------------
Originally neither the LatticeMico32 nor its peripherals support a
mechanism to shut down the machine. Emulation aware programs can write to a
to a special register within the system control block to shut down the
virtual machine.  For more details see hw/lm32_sys.c. The lm32-evr is the
first BSP which instantiate this model. A (32 bit) write to 0xfff0000
causes a vm shutdown.


Special instructions
--------------------
The translation recognizes one special instruction to halt the cpu:
  and r0, r0, r0
On real hardware this instruction is a nop. It is not used by GCC and
should (hopefully) not be used within hand-crafted assembly.
Insert this instruction in your idle loop to reduce the cpu load on the
host.


Ignoring the MSB of the address bus
-----------------------------------
Some SoC ignores the MSB on the address bus. Thus creating a shadow memory
area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
0x80000000-0xffffffff is not cached and used to access IO devices. This
behaviour can be enabled with:
  cpu_lm32_set_phys_msb_ignore(env, 1);