2656eb7c59
* fix preferred return address for A64 BRK insn * implement AArch64 single-stepping * support loading gzip compressed AArch64 kernels * use correct PSCI function IDs in the DT when KVM uses PSCI 0.2 * minor cleanups -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJT85GZAAoJEDwlJe0UNgzeSpQP/1/m2nJxDvyKWRsNhk4CObsk Ex/HI850B1tOlv8c14jIG0kCg0n5SKrSmNSkIqtaZuykRCUk0F2TZAn6uvKaPxqO Xy40HBrdji2FPLk8mKvc0QY3ucV9BsYiPNBQNVqnctlmLeTtcs3ufFFmchC3Damz euCDIhCvT4KlyQz7s7WeM8RIA0ugJIpX/umc+GR853vYPixLInQGoRcWEaKfBTEy BYLl/LN8MYMxGgNALUf4ErVrReCg3h8485m5GHRb/I+42w62pyI1wKLlkrcEOwhk w0JsemPRTyY7QPOHLCwxMKIq4Idil55vNpvLC2qUuig+SWHqfQjhhy4W6NvqkMWJ uorgm6WA2C6K1lLMzMtwRjzQQUB+ct7KDUbcO7Z4638X8ACnALP0tzl1n0NZvvPJ EN6CQrfWeKmd7VWnCRd5JEvTgQZlwsC9mg8Tob1MamoqzGj4JWnZzVsoP1sE+g+6 xnglHysQrcjSeYh6RFvbkwv9jZLS4NKJUN3Zgm1S2G+zNT5aK9akEmSpAq2B/mxA f2KlI9lSvPbj2JA6ichxxCGr1sgX1PJwLQd5gPLrmEXaGUEGmq4gz1h3mmZdd1wZ Uwo9qNCA/RUdkxuLJ93CL/we02kp2cZwN2pjYGWomTkc3VLGCYaaITkIeq+LNG+L uPxVdmOUK/05QWrT8gC6 =+uR+ -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140819' into staging target-arm: * fix preferred return address for A64 BRK insn * implement AArch64 single-stepping * support loading gzip compressed AArch64 kernels * use correct PSCI function IDs in the DT when KVM uses PSCI 0.2 * minor cleanups # gpg: Signature made Tue 19 Aug 2014 19:04:09 BST using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20140819: arm: stellaris: Remove misleading address_space_mem var arm: armv7m: Rename address_space_mem -> system_memory aarch64: Allow -kernel option to take a gzip-compressed kernel. loader: Add load_image_gzipped function. arm: cortex-a9: Fix cache-line size and associativity arm/virt: Use PSCI v0.2 function IDs in the DT when KVM uses PSCI v0.2 target-arm: Rename QEMU PSCI v0.1 definitions target-arm: Implement MDSCR_EL1 as having state target-arm: Implement ARMv8 single-stepping for AArch32 code target-arm: Implement ARMv8 single-step handling for A64 code target-arm: A64: Avoid duplicate exit_tb(0) in non-linked goto_tb target-arm: Set PSTATE.SS correctly on exception return from AArch64 target-arm: Correctly handle PSTATE.SS when taking exception to AArch32 target-arm: Don't allow AArch32 to access RES0 CPSR bits target-arm: Adjust debug ID registers per-CPU target-arm: Provide both 32 and 64 bit versions of debug registers target-arm: Allow STATE_BOTH reginfo descriptions for more than cp14 target-arm: Collect up the debug cp register definitions target-arm: Fix return address for A64 BRK instructions Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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