Philippe Mathieu-Daudé 298d43c96b target/mips: Add missing CP0 check to nanoMIPS RDPGPR / WRPGPR opcodes ... Per the nanoMIPS32 Instruction Set Technical Reference Manual, Revision 01.01, Chapter 3. "Instruction Definitions": The Read/Write Previous GPR opcodes "require CP0 privilege". Add the missing CP0 checks. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210421185007.2231855-1-f4bug@amsat.org>		2021-05-02 16:49:34 +02:00
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alpha	target/alpha: fix icount handling for timer instructions	2021-04-05 07:32:56 -07:00
arm	target/arm: Enforce alignment for sve LD1R	2021-04-30 11:16:51 +01:00
avr	target/avr: Fix interrupt execution	2021-03-15 00:39:52 +01:00
cris
hexagon	hexagon: do not specify Python scripts as inputs	2021-04-01 10:37:20 +02:00
hppa
i386	i386: Add missing cpu feature bits in EPYC-Rome model	2021-04-09 16:02:18 -04:00
lm32
m68k	Prepare MacOS ROM support:	2021-03-12 18:56:56 +00:00
microblaze
mips	target/mips: Add missing CP0 check to nanoMIPS RDPGPR / WRPGPR opcodes	2021-05-02 16:49:34 +02:00
moxie
nios2
openrisc	target/openrisc: fix icount handling for timer instructions	2021-04-01 10:37:20 +02:00
ppc	target/ppc/kvm: Cache timebase frequency	2021-03-31 11:10:50 +11:00
riscv	target/riscv: Prevent lost illegal instruction exceptions	2021-03-22 21:54:40 -04:00
rx
s390x	target/s390x: fix s390_probe_access to check PAGE_WRITE_ORG for writeability	2021-04-23 14:10:56 +01:00
sh4
sparc
tricore	target/tricore: Fix OPC2_32_RRPW_EXTR for width=0	2021-03-14 14:49:01 +01:00
unicore32
xtensa	target/xtensa: make xtensa_modules static on import	2021-04-03 08:52:18 -07:00
meson.build