1c8a2388aa
The SCU is a collection of chip-level control registers that manage the various functions supported by ASPEED SoCs. Typically the bits control interactions with clocks, external hardware or reset behaviour, and we can largly take a hands-off approach to reads and writes. Firmware makes heavy use of the state to determine how to boot, but the reset values vary from SoC to SoC (eg AST2400 vs AST2500). A qdev property is exposed so that the integrating SoC model can configure the silicon revision, which in-turn selects the appropriate reset values. Further qdev properties are exposed so the board model can configure the board-dependent hardware strapping. Almost all provided AST2400 reset values are specified by the datasheet. The notable exception is SOC_SCRATCH1, where we mark the DRAM as successfully initialised to avoid unnecessary dark corners in the SoC's u-boot support. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1466744305-23163-2-git-send-email-andrew@aj.id.au Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: drop unnecessary inttypes.h include] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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| .. | ||
| a9scu.h | ||
| arm11scu.h | ||
| arm_integrator_debug.h | ||
| aspeed_scu.h | ||
| aux.h | ||
| bcm2835_mbox_defs.h | ||
| bcm2835_mbox.h | ||
| bcm2835_property.h | ||
| imx6_ccm.h | ||
| imx6_src.h | ||
| imx25_ccm.h | ||
| imx31_ccm.h | ||
| imx_ccm.h | ||
| ivshmem.h | ||
| mips_cmgcr.h | ||
| mips_cpc.h | ||
| mips_itu.h | ||
| stm32f2xx_syscfg.h | ||
| tmp105_regs.h | ||
| zynq-xadc.h | ||