qemu-e2k/target-mips
ths 01179c382b Kill broken host register definitions, thanks to Paul Brook and Herve
Poussineau for debugging this.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2747 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-29 21:26:37 +00:00
..
TODO Update TODO. 2007-04-28 21:44:04 +00:00
cpu.h Choose number of TLBs at runtime, by Herve Poussineau. 2007-04-17 15:26:47 +00:00
exec.h Kill broken host register definitions, thanks to Paul Brook and Herve 2007-04-29 21:26:37 +00:00
fop_template.c Preliminiary MIPS64 support, disabled by default due to performance impact. 2006-12-21 01:19:56 +00:00
helper.c Another fix for CP0 Cause register handling. 2007-04-13 20:17:54 +00:00
mips-defs.h Kill broken host register definitions, thanks to Paul Brook and Herve 2007-04-29 21:26:37 +00:00
op.c Choose number of TLBs at runtime, by Herve Poussineau. 2007-04-17 15:26:47 +00:00
op_helper.c Choose number of TLBs at runtime, by Herve Poussineau. 2007-04-17 15:26:47 +00:00
op_helper_mem.c Actually enable 64bit configuration. 2007-04-01 12:36:18 +00:00
op_mem.c Catch unaligned sc/scd. 2007-04-09 14:14:21 +00:00
op_template.c Revert last checkin. 2007-04-29 21:19:03 +00:00
translate.c Next attempt to get the lui sign extension right. 2007-04-25 16:41:11 +00:00
translate_init.c Choose number of TLBs at runtime, by Herve Poussineau. 2007-04-17 15:26:47 +00:00