Jonathan Cameron 314f5033c6 hw/pci-bridge/cxl_downstream: Set default link width and link speed ... Without these being set the PCIE Link Capabilities register has invalid values in these two fields. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20231023160806.13206-10-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>		2023-11-07 03:39:11 -05:00
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cxl_downstream.c	hw/pci-bridge/cxl_downstream: Set default link width and link speed	2023-11-07 03:39:11 -05:00
cxl_root_port.c	hw/cxl: CXLDVSECPortExtensions renamed to CXLDVSECPortExt	2023-11-07 03:39:11 -05:00
cxl_upstream.c	hw/pci-bridge/cxl_upstream: Move defintion of device to header.	2023-11-07 03:39:11 -05:00
gen_pcie_root_port.c
i82801b11.c
ioh3420.c
Kconfig	hw/pci-bridge: make building pcie-to-pci bridge configurable	2023-05-19 10:30:46 -04:00
meson.build	meson: Replace softmmu_ss -> system_ss	2023-06-20 10:01:30 +02:00
pci_bridge_dev.c
pci_expander_bridge_stubs.c
pci_expander_bridge.c	hw/pci: spelling fixes	2023-09-20 07:54:34 +03:00
pcie_pci_bridge.c
pcie_root_port.c
simba.c
xio3130_downstream.c
xio3130_upstream.c