bf4460a8d9
tcg: Avoid recursion in tcg_gen_mulu2_i32 tcg: Mark tcg helpers noinline to avoid an issue with LTO tcg/arm: Use register pair allocation for qemu_{ld,st}_i64 disas: Enable loongarch disassembler, and fixes tcg/loongarch64: Improve move immediate tcg/loongarch64: Improve add immediate tcg/loongarch64: Improve setcond tcg/loongarch64: Implement movcond tcg/loongarch64: Use tcg_pcrel_diff in tcg_out_ldst tcg/loongarch64: Reorg goto_tb implementation -----BEGIN PGP SIGNATURE----- iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmPPO+0dHHJpY2hhcmQu aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV93jwgAhG+H5XHtJqF2isCc a6pYuUWRbhsOFL23FmWKx2O41tHlJ2Seort8M9eIHOu21L9DUJFd291O/4ckiMQM 13+KH/Kl5fumM+uEkO9YMyplOddmvygdTd5dCi5y349Gi3CgJH3n4HUl0qnioM/7 Dy3n8JIvYsBp+8jUsLXo1gSl5P1kLMLwJmP68qgy8z8Xly4bDco1Nb2UKb7qKevO lMr6L+2/ALbKLZ6OU50erdUrlbgNs0eiQyJAfJ47SQ57RGuqF4pZ09+9yRI2FPZt UlSn+srsec1ieYyM2e5krVWbNcXaj6FouV7CkbgFXoUZt29xA1HTXsso+8vLgDPu g8vvuw== =Up0b -----END PGP SIGNATURE----- Merge tag 'pull-tcg-20230123' of https://gitlab.com/rth7680/qemu into staging common-user: Re-enable ppc32 host tcg: Avoid recursion in tcg_gen_mulu2_i32 tcg: Mark tcg helpers noinline to avoid an issue with LTO tcg/arm: Use register pair allocation for qemu_{ld,st}_i64 disas: Enable loongarch disassembler, and fixes tcg/loongarch64: Improve move immediate tcg/loongarch64: Improve add immediate tcg/loongarch64: Improve setcond tcg/loongarch64: Implement movcond tcg/loongarch64: Use tcg_pcrel_diff in tcg_out_ldst tcg/loongarch64: Reorg goto_tb implementation # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmPPO+0dHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV93jwgAhG+H5XHtJqF2isCc # a6pYuUWRbhsOFL23FmWKx2O41tHlJ2Seort8M9eIHOu21L9DUJFd291O/4ckiMQM # 13+KH/Kl5fumM+uEkO9YMyplOddmvygdTd5dCi5y349Gi3CgJH3n4HUl0qnioM/7 # Dy3n8JIvYsBp+8jUsLXo1gSl5P1kLMLwJmP68qgy8z8Xly4bDco1Nb2UKb7qKevO # lMr6L+2/ALbKLZ6OU50erdUrlbgNs0eiQyJAfJ47SQ57RGuqF4pZ09+9yRI2FPZt # UlSn+srsec1ieYyM2e5krVWbNcXaj6FouV7CkbgFXoUZt29xA1HTXsso+8vLgDPu # g8vvuw== # =Up0b # -----END PGP SIGNATURE----- # gpg: Signature made Tue 24 Jan 2023 02:01:17 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20230123' of https://gitlab.com/rth7680/qemu: tcg/loongarch64: Reorg goto_tb implementation tcg/loongarch64: Use tcg_pcrel_diff in tcg_out_ldst tcg/loongarch64: Implement movcond tcg/loongarch64: Improve setcond expansion tcg/loongarch64: Introduce tcg_out_addi tcg/loongarch64: Update tcg-insn-defs.c.inc tcg/loongarch64: Optimize immediate loading target/loongarch: Disassemble pcadd* addresses target/loongarch: Disassemble jirl properly target/loongarch: Enable the disassembler for host tcg tcg: Mark tcg helpers noinline to avoid an issue with LTO linux-user: Implment host/ppc/host-signal.h common-user/host/ppc: Implement safe-syscall.inc.S tcg/arm: Use register pair allocation for qemu_{ld,st}_i64 tcg: Avoid recursion in tcg_gen_mulu2_i32 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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.. | ||
aarch64 | ||
arm | ||
i386 | ||
loongarch64 | ||
mips | ||
ppc | ||
riscv | ||
s390x | ||
sparc64 | ||
tci | ||
meson.build | ||
optimize.c | ||
region.c | ||
tcg-common.c | ||
tcg-internal.h | ||
tcg-ldst.c.inc | ||
tcg-op-gvec.c | ||
tcg-op-vec.c | ||
tcg-op.c | ||
tcg-pool.c.inc | ||
tcg.c | ||
tci.c |