1200 lines
41 KiB
C
1200 lines
41 KiB
C
/*
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* i386 emulator main execution loop
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "config.h"
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#include "exec.h"
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#include "disas.h"
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#include "tcg.h"
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#include "kvm.h"
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#if !defined(CONFIG_SOFTMMU)
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#undef EAX
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#undef ECX
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#undef EDX
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#undef EBX
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#undef ESP
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#undef EBP
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#undef ESI
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#undef EDI
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#undef EIP
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#include <signal.h>
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#ifdef __linux__
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#include <sys/ucontext.h>
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#endif
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#endif
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#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
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// Work around ugly bugs in glibc that mangle global register contents
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#undef env
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#define env cpu_single_env
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#endif
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int tb_invalidated_flag;
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//#define CONFIG_DEBUG_EXEC
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//#define DEBUG_SIGNAL
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int qemu_cpu_has_work(CPUState *env)
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{
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return cpu_has_work(env);
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}
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void cpu_loop_exit(void)
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{
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/* NOTE: the register at this point must be saved by hand because
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longjmp restore them */
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regs_to_env();
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longjmp(env->jmp_env, 1);
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}
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/* exit the current TB from a signal handler. The host registers are
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restored in a state compatible with the CPU emulator
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*/
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void cpu_resume_from_signal(CPUState *env1, void *puc)
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{
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#if !defined(CONFIG_SOFTMMU)
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#ifdef __linux__
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struct ucontext *uc = puc;
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#elif defined(__OpenBSD__)
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struct sigcontext *uc = puc;
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#endif
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#endif
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env = env1;
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/* XXX: restore cpu registers saved in host registers */
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#if !defined(CONFIG_SOFTMMU)
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if (puc) {
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/* XXX: use siglongjmp ? */
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#ifdef __linux__
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sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
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#elif defined(__OpenBSD__)
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sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
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#endif
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}
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#endif
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env->exception_index = -1;
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longjmp(env->jmp_env, 1);
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}
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/* Execute the code without caching the generated code. An interpreter
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could be used if available. */
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static void cpu_exec_nocache(int max_cycles, TranslationBlock *orig_tb)
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{
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unsigned long next_tb;
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TranslationBlock *tb;
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/* Should never happen.
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We only end up here when an existing TB is too long. */
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if (max_cycles > CF_COUNT_MASK)
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max_cycles = CF_COUNT_MASK;
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tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
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max_cycles);
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env->current_tb = tb;
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/* execute the generated code */
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next_tb = tcg_qemu_tb_exec(tb->tc_ptr);
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if ((next_tb & 3) == 2) {
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/* Restore PC. This may happen if async event occurs before
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the TB starts executing. */
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cpu_pc_from_tb(env, tb);
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}
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tb_phys_invalidate(tb, -1);
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tb_free(tb);
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}
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static TranslationBlock *tb_find_slow(target_ulong pc,
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target_ulong cs_base,
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uint64_t flags)
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{
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TranslationBlock *tb, **ptb1;
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unsigned int h;
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target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
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tb_invalidated_flag = 0;
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regs_to_env(); /* XXX: do it just before cpu_gen_code() */
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/* find translated block using physical mappings */
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phys_pc = get_phys_addr_code(env, pc);
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phys_page1 = phys_pc & TARGET_PAGE_MASK;
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phys_page2 = -1;
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h = tb_phys_hash_func(phys_pc);
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ptb1 = &tb_phys_hash[h];
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for(;;) {
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tb = *ptb1;
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if (!tb)
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goto not_found;
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if (tb->pc == pc &&
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tb->page_addr[0] == phys_page1 &&
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tb->cs_base == cs_base &&
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tb->flags == flags) {
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/* check next page if needed */
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if (tb->page_addr[1] != -1) {
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virt_page2 = (pc & TARGET_PAGE_MASK) +
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TARGET_PAGE_SIZE;
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phys_page2 = get_phys_addr_code(env, virt_page2);
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if (tb->page_addr[1] == phys_page2)
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goto found;
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} else {
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goto found;
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}
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}
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ptb1 = &tb->phys_hash_next;
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}
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not_found:
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/* if no translated code available, then translate it now */
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tb = tb_gen_code(env, pc, cs_base, flags, 0);
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found:
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/* we add the TB in the virtual pc hash table */
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env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
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return tb;
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}
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static inline TranslationBlock *tb_find_fast(void)
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{
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TranslationBlock *tb;
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target_ulong cs_base, pc;
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int flags;
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/* we record a subset of the CPU state. It will
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always be the same before a given translated block
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is executed. */
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cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
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tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
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if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
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tb->flags != flags)) {
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tb = tb_find_slow(pc, cs_base, flags);
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}
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return tb;
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}
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static CPUDebugExcpHandler *debug_excp_handler;
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CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler)
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{
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CPUDebugExcpHandler *old_handler = debug_excp_handler;
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debug_excp_handler = handler;
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return old_handler;
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}
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static void cpu_handle_debug_exception(CPUState *env)
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{
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CPUWatchpoint *wp;
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if (!env->watchpoint_hit)
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QTAILQ_FOREACH(wp, &env->watchpoints, entry)
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wp->flags &= ~BP_WATCHPOINT_HIT;
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if (debug_excp_handler)
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debug_excp_handler(env);
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}
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/* main execution loop */
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int cpu_exec(CPUState *env1)
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{
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#define DECLARE_HOST_REGS 1
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#include "hostregs_helper.h"
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int ret, interrupt_request;
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TranslationBlock *tb;
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uint8_t *tc_ptr;
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unsigned long next_tb;
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if (cpu_halted(env1) == EXCP_HALTED)
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return EXCP_HALTED;
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cpu_single_env = env1;
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/* first we save global registers */
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#define SAVE_HOST_REGS 1
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#include "hostregs_helper.h"
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env = env1;
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env_to_regs();
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#if defined(TARGET_I386)
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/* put eflags in CPU temporary format */
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CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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DF = 1 - (2 * ((env->eflags >> 10) & 1));
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CC_OP = CC_OP_EFLAGS;
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env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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#elif defined(TARGET_SPARC)
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#elif defined(TARGET_M68K)
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env->cc_op = CC_OP_FLAGS;
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env->cc_dest = env->sr & 0xf;
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env->cc_x = (env->sr >> 4) & 1;
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#elif defined(TARGET_ALPHA)
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#elif defined(TARGET_ARM)
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#elif defined(TARGET_PPC)
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#elif defined(TARGET_MICROBLAZE)
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#elif defined(TARGET_MIPS)
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#elif defined(TARGET_SH4)
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#elif defined(TARGET_CRIS)
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/* XXXXX */
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#else
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#error unsupported target CPU
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#endif
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env->exception_index = -1;
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/* prepare setjmp context for exception handling */
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for(;;) {
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if (setjmp(env->jmp_env) == 0) {
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#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
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#undef env
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env = cpu_single_env;
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#define env cpu_single_env
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#endif
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env->current_tb = NULL;
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/* if an exception is pending, we execute it here */
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if (env->exception_index >= 0) {
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if (env->exception_index >= EXCP_INTERRUPT) {
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/* exit request from the cpu execution loop */
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ret = env->exception_index;
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if (ret == EXCP_DEBUG)
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cpu_handle_debug_exception(env);
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break;
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} else {
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#if defined(CONFIG_USER_ONLY)
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/* if user mode only, we simulate a fake exception
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which will be handled outside the cpu execution
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loop */
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#if defined(TARGET_I386)
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do_interrupt_user(env->exception_index,
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env->exception_is_int,
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env->error_code,
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env->exception_next_eip);
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/* successfully delivered */
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env->old_exception = -1;
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#endif
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ret = env->exception_index;
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break;
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#else
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#if defined(TARGET_I386)
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/* simulate a real cpu exception. On i386, it can
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trigger new exceptions, but we do not handle
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double or triple faults yet. */
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do_interrupt(env->exception_index,
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env->exception_is_int,
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env->error_code,
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env->exception_next_eip, 0);
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/* successfully delivered */
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env->old_exception = -1;
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#elif defined(TARGET_PPC)
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do_interrupt(env);
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#elif defined(TARGET_MICROBLAZE)
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do_interrupt(env);
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#elif defined(TARGET_MIPS)
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do_interrupt(env);
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#elif defined(TARGET_SPARC)
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do_interrupt(env);
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#elif defined(TARGET_ARM)
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do_interrupt(env);
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#elif defined(TARGET_SH4)
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do_interrupt(env);
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#elif defined(TARGET_ALPHA)
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do_interrupt(env);
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#elif defined(TARGET_CRIS)
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do_interrupt(env);
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#elif defined(TARGET_M68K)
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do_interrupt(0);
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#endif
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#endif
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}
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env->exception_index = -1;
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}
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if (kvm_enabled()) {
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kvm_cpu_exec(env);
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longjmp(env->jmp_env, 1);
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}
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next_tb = 0; /* force lookup of first TB */
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for(;;) {
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interrupt_request = env->interrupt_request;
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if (unlikely(interrupt_request)) {
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if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
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/* Mask out external interrupts for this step. */
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interrupt_request &= ~(CPU_INTERRUPT_HARD |
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CPU_INTERRUPT_FIQ |
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CPU_INTERRUPT_SMI |
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CPU_INTERRUPT_NMI);
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}
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if (interrupt_request & CPU_INTERRUPT_DEBUG) {
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env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
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env->exception_index = EXCP_DEBUG;
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cpu_loop_exit();
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}
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#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
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defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
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defined(TARGET_MICROBLAZE)
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if (interrupt_request & CPU_INTERRUPT_HALT) {
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env->interrupt_request &= ~CPU_INTERRUPT_HALT;
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env->halted = 1;
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env->exception_index = EXCP_HLT;
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cpu_loop_exit();
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}
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#endif
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#if defined(TARGET_I386)
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if (interrupt_request & CPU_INTERRUPT_INIT) {
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svm_check_intercept(SVM_EXIT_INIT);
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do_cpu_init(env);
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env->exception_index = EXCP_HALTED;
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cpu_loop_exit();
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} else if (interrupt_request & CPU_INTERRUPT_SIPI) {
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do_cpu_sipi(env);
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} else if (env->hflags2 & HF2_GIF_MASK) {
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if ((interrupt_request & CPU_INTERRUPT_SMI) &&
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!(env->hflags & HF_SMM_MASK)) {
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svm_check_intercept(SVM_EXIT_SMI);
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env->interrupt_request &= ~CPU_INTERRUPT_SMI;
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do_smm_enter();
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next_tb = 0;
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} else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
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!(env->hflags2 & HF2_NMI_MASK)) {
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env->interrupt_request &= ~CPU_INTERRUPT_NMI;
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env->hflags2 |= HF2_NMI_MASK;
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do_interrupt(EXCP02_NMI, 0, 0, 0, 1);
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next_tb = 0;
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} else if (interrupt_request & CPU_INTERRUPT_MCE) {
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env->interrupt_request &= ~CPU_INTERRUPT_MCE;
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do_interrupt(EXCP12_MCHK, 0, 0, 0, 0);
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next_tb = 0;
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} else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
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(((env->hflags2 & HF2_VINTR_MASK) &&
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(env->hflags2 & HF2_HIF_MASK)) ||
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(!(env->hflags2 & HF2_VINTR_MASK) &&
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(env->eflags & IF_MASK &&
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!(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
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int intno;
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svm_check_intercept(SVM_EXIT_INTR);
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env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ);
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intno = cpu_get_pic_interrupt(env);
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qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno);
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#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
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#undef env
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env = cpu_single_env;
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#define env cpu_single_env
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#endif
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do_interrupt(intno, 0, 0, 0, 1);
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/* ensure that no TB jump will be modified as
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the program flow was changed */
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next_tb = 0;
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#if !defined(CONFIG_USER_ONLY)
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} else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
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(env->eflags & IF_MASK) &&
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!(env->hflags & HF_INHIBIT_IRQ_MASK)) {
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int intno;
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/* FIXME: this should respect TPR */
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svm_check_intercept(SVM_EXIT_VINTR);
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intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
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qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno);
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do_interrupt(intno, 0, 0, 0, 1);
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env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
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next_tb = 0;
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#endif
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}
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}
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#elif defined(TARGET_PPC)
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#if 0
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if ((interrupt_request & CPU_INTERRUPT_RESET)) {
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cpu_reset(env);
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}
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#endif
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if (interrupt_request & CPU_INTERRUPT_HARD) {
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ppc_hw_interrupt(env);
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if (env->pending_interrupts == 0)
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env->interrupt_request &= ~CPU_INTERRUPT_HARD;
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next_tb = 0;
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}
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#elif defined(TARGET_MICROBLAZE)
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if ((interrupt_request & CPU_INTERRUPT_HARD)
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&& (env->sregs[SR_MSR] & MSR_IE)
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&& !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
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&& !(env->iflags & (D_FLAG | IMM_FLAG))) {
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env->exception_index = EXCP_IRQ;
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do_interrupt(env);
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next_tb = 0;
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}
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#elif defined(TARGET_MIPS)
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if ((interrupt_request & CPU_INTERRUPT_HARD) &&
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(env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
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(env->CP0_Status & (1 << CP0St_IE)) &&
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!(env->CP0_Status & (1 << CP0St_EXL)) &&
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!(env->CP0_Status & (1 << CP0St_ERL)) &&
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!(env->hflags & MIPS_HFLAG_DM)) {
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/* Raise it */
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env->exception_index = EXCP_EXT_INTERRUPT;
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env->error_code = 0;
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do_interrupt(env);
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next_tb = 0;
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}
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#elif defined(TARGET_SPARC)
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if ((interrupt_request & CPU_INTERRUPT_HARD) &&
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cpu_interrupts_enabled(env)) {
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int pil = env->interrupt_index & 15;
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int type = env->interrupt_index & 0xf0;
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if (((type == TT_EXTINT) &&
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(pil == 15 || pil > env->psrpil)) ||
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type != TT_EXTINT) {
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env->interrupt_request &= ~CPU_INTERRUPT_HARD;
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env->exception_index = env->interrupt_index;
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do_interrupt(env);
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env->interrupt_index = 0;
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next_tb = 0;
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}
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} else if (interrupt_request & CPU_INTERRUPT_TIMER) {
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//do_interrupt(0, 0, 0, 0, 0);
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env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
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}
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#elif defined(TARGET_ARM)
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if (interrupt_request & CPU_INTERRUPT_FIQ
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&& !(env->uncached_cpsr & CPSR_F)) {
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env->exception_index = EXCP_FIQ;
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do_interrupt(env);
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next_tb = 0;
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}
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/* ARMv7-M interrupt return works by loading a magic value
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into the PC. On real hardware the load causes the
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return to occur. The qemu implementation performs the
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jump normally, then does the exception return when the
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CPU tries to execute code at the magic address.
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This will cause the magic PC value to be pushed to
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the stack if an interrupt occured at the wrong time.
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We avoid this by disabling interrupts when
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pc contains a magic address. */
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if (interrupt_request & CPU_INTERRUPT_HARD
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&& ((IS_M(env) && env->regs[15] < 0xfffffff0)
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|
|| !(env->uncached_cpsr & CPSR_I))) {
|
|
env->exception_index = EXCP_IRQ;
|
|
do_interrupt(env);
|
|
next_tb = 0;
|
|
}
|
|
#elif defined(TARGET_SH4)
|
|
if (interrupt_request & CPU_INTERRUPT_HARD) {
|
|
do_interrupt(env);
|
|
next_tb = 0;
|
|
}
|
|
#elif defined(TARGET_ALPHA)
|
|
if (interrupt_request & CPU_INTERRUPT_HARD) {
|
|
do_interrupt(env);
|
|
next_tb = 0;
|
|
}
|
|
#elif defined(TARGET_CRIS)
|
|
if (interrupt_request & CPU_INTERRUPT_HARD
|
|
&& (env->pregs[PR_CCS] & I_FLAG)) {
|
|
env->exception_index = EXCP_IRQ;
|
|
do_interrupt(env);
|
|
next_tb = 0;
|
|
}
|
|
if (interrupt_request & CPU_INTERRUPT_NMI
|
|
&& (env->pregs[PR_CCS] & M_FLAG)) {
|
|
env->exception_index = EXCP_NMI;
|
|
do_interrupt(env);
|
|
next_tb = 0;
|
|
}
|
|
#elif defined(TARGET_M68K)
|
|
if (interrupt_request & CPU_INTERRUPT_HARD
|
|
&& ((env->sr & SR_I) >> SR_I_SHIFT)
|
|
< env->pending_level) {
|
|
/* Real hardware gets the interrupt vector via an
|
|
IACK cycle at this point. Current emulated
|
|
hardware doesn't rely on this, so we
|
|
provide/save the vector when the interrupt is
|
|
first signalled. */
|
|
env->exception_index = env->pending_vector;
|
|
do_interrupt(1);
|
|
next_tb = 0;
|
|
}
|
|
#endif
|
|
/* Don't use the cached interupt_request value,
|
|
do_interrupt may have updated the EXITTB flag. */
|
|
if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
|
|
env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
|
|
/* ensure that no TB jump will be modified as
|
|
the program flow was changed */
|
|
next_tb = 0;
|
|
}
|
|
}
|
|
if (unlikely(env->exit_request)) {
|
|
env->exit_request = 0;
|
|
env->exception_index = EXCP_INTERRUPT;
|
|
cpu_loop_exit();
|
|
}
|
|
#ifdef CONFIG_DEBUG_EXEC
|
|
if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
|
|
/* restore flags in standard format */
|
|
regs_to_env();
|
|
#if defined(TARGET_I386)
|
|
env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
|
|
log_cpu_state(env, X86_DUMP_CCOP);
|
|
env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
|
|
#elif defined(TARGET_ARM)
|
|
log_cpu_state(env, 0);
|
|
#elif defined(TARGET_SPARC)
|
|
log_cpu_state(env, 0);
|
|
#elif defined(TARGET_PPC)
|
|
log_cpu_state(env, 0);
|
|
#elif defined(TARGET_M68K)
|
|
cpu_m68k_flush_flags(env, env->cc_op);
|
|
env->cc_op = CC_OP_FLAGS;
|
|
env->sr = (env->sr & 0xffe0)
|
|
| env->cc_dest | (env->cc_x << 4);
|
|
log_cpu_state(env, 0);
|
|
#elif defined(TARGET_MICROBLAZE)
|
|
log_cpu_state(env, 0);
|
|
#elif defined(TARGET_MIPS)
|
|
log_cpu_state(env, 0);
|
|
#elif defined(TARGET_SH4)
|
|
log_cpu_state(env, 0);
|
|
#elif defined(TARGET_ALPHA)
|
|
log_cpu_state(env, 0);
|
|
#elif defined(TARGET_CRIS)
|
|
log_cpu_state(env, 0);
|
|
#else
|
|
#error unsupported target CPU
|
|
#endif
|
|
}
|
|
#endif
|
|
spin_lock(&tb_lock);
|
|
tb = tb_find_fast();
|
|
/* Note: we do it here to avoid a gcc bug on Mac OS X when
|
|
doing it in tb_find_slow */
|
|
if (tb_invalidated_flag) {
|
|
/* as some TB could have been invalidated because
|
|
of memory exceptions while generating the code, we
|
|
must recompute the hash index here */
|
|
next_tb = 0;
|
|
tb_invalidated_flag = 0;
|
|
}
|
|
#ifdef CONFIG_DEBUG_EXEC
|
|
qemu_log_mask(CPU_LOG_EXEC, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
|
|
(long)tb->tc_ptr, tb->pc,
|
|
lookup_symbol(tb->pc));
|
|
#endif
|
|
/* see if we can patch the calling TB. When the TB
|
|
spans two pages, we cannot safely do a direct
|
|
jump. */
|
|
{
|
|
if (next_tb != 0 && tb->page_addr[1] == -1) {
|
|
tb_add_jump((TranslationBlock *)(next_tb & ~3), next_tb & 3, tb);
|
|
}
|
|
}
|
|
spin_unlock(&tb_lock);
|
|
env->current_tb = tb;
|
|
|
|
/* cpu_interrupt might be called while translating the
|
|
TB, but before it is linked into a potentially
|
|
infinite loop and becomes env->current_tb. Avoid
|
|
starting execution if there is a pending interrupt. */
|
|
if (unlikely (env->exit_request))
|
|
env->current_tb = NULL;
|
|
|
|
while (env->current_tb) {
|
|
tc_ptr = tb->tc_ptr;
|
|
/* execute the generated code */
|
|
#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
|
|
#undef env
|
|
env = cpu_single_env;
|
|
#define env cpu_single_env
|
|
#endif
|
|
next_tb = tcg_qemu_tb_exec(tc_ptr);
|
|
env->current_tb = NULL;
|
|
if ((next_tb & 3) == 2) {
|
|
/* Instruction counter expired. */
|
|
int insns_left;
|
|
tb = (TranslationBlock *)(long)(next_tb & ~3);
|
|
/* Restore PC. */
|
|
cpu_pc_from_tb(env, tb);
|
|
insns_left = env->icount_decr.u32;
|
|
if (env->icount_extra && insns_left >= 0) {
|
|
/* Refill decrementer and continue execution. */
|
|
env->icount_extra += insns_left;
|
|
if (env->icount_extra > 0xffff) {
|
|
insns_left = 0xffff;
|
|
} else {
|
|
insns_left = env->icount_extra;
|
|
}
|
|
env->icount_extra -= insns_left;
|
|
env->icount_decr.u16.low = insns_left;
|
|
} else {
|
|
if (insns_left > 0) {
|
|
/* Execute remaining instructions. */
|
|
cpu_exec_nocache(insns_left, tb);
|
|
}
|
|
env->exception_index = EXCP_INTERRUPT;
|
|
next_tb = 0;
|
|
cpu_loop_exit();
|
|
}
|
|
}
|
|
}
|
|
/* reset soft MMU for next block (it can currently
|
|
only be set by a memory fault) */
|
|
} /* for(;;) */
|
|
} else {
|
|
env_to_regs();
|
|
}
|
|
} /* for(;;) */
|
|
|
|
|
|
#if defined(TARGET_I386)
|
|
/* restore flags in standard format */
|
|
env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
|
|
#elif defined(TARGET_ARM)
|
|
/* XXX: Save/restore host fpu exception state?. */
|
|
#elif defined(TARGET_SPARC)
|
|
#elif defined(TARGET_PPC)
|
|
#elif defined(TARGET_M68K)
|
|
cpu_m68k_flush_flags(env, env->cc_op);
|
|
env->cc_op = CC_OP_FLAGS;
|
|
env->sr = (env->sr & 0xffe0)
|
|
| env->cc_dest | (env->cc_x << 4);
|
|
#elif defined(TARGET_MICROBLAZE)
|
|
#elif defined(TARGET_MIPS)
|
|
#elif defined(TARGET_SH4)
|
|
#elif defined(TARGET_ALPHA)
|
|
#elif defined(TARGET_CRIS)
|
|
/* XXXXX */
|
|
#else
|
|
#error unsupported target CPU
|
|
#endif
|
|
|
|
/* restore global registers */
|
|
#include "hostregs_helper.h"
|
|
|
|
/* fail safe : never use cpu_single_env outside cpu_exec() */
|
|
cpu_single_env = NULL;
|
|
return ret;
|
|
}
|
|
|
|
/* must only be called from the generated code as an exception can be
|
|
generated */
|
|
void tb_invalidate_page_range(target_ulong start, target_ulong end)
|
|
{
|
|
/* XXX: cannot enable it yet because it yields to MMU exception
|
|
where NIP != read address on PowerPC */
|
|
#if 0
|
|
target_ulong phys_addr;
|
|
phys_addr = get_phys_addr_code(env, start);
|
|
tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
|
|
#endif
|
|
}
|
|
|
|
#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
|
|
|
|
void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
|
|
{
|
|
CPUX86State *saved_env;
|
|
|
|
saved_env = env;
|
|
env = s;
|
|
if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
|
|
selector &= 0xffff;
|
|
cpu_x86_load_seg_cache(env, seg_reg, selector,
|
|
(selector << 4), 0xffff, 0);
|
|
} else {
|
|
helper_load_seg(seg_reg, selector);
|
|
}
|
|
env = saved_env;
|
|
}
|
|
|
|
void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32)
|
|
{
|
|
CPUX86State *saved_env;
|
|
|
|
saved_env = env;
|
|
env = s;
|
|
|
|
helper_fsave(ptr, data32);
|
|
|
|
env = saved_env;
|
|
}
|
|
|
|
void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32)
|
|
{
|
|
CPUX86State *saved_env;
|
|
|
|
saved_env = env;
|
|
env = s;
|
|
|
|
helper_frstor(ptr, data32);
|
|
|
|
env = saved_env;
|
|
}
|
|
|
|
#endif /* TARGET_I386 */
|
|
|
|
#if !defined(CONFIG_SOFTMMU)
|
|
|
|
#if defined(TARGET_I386)
|
|
#define EXCEPTION_ACTION raise_exception_err(env->exception_index, env->error_code)
|
|
#else
|
|
#define EXCEPTION_ACTION cpu_loop_exit()
|
|
#endif
|
|
|
|
/* 'pc' is the host PC at which the exception was raised. 'address' is
|
|
the effective address of the memory exception. 'is_write' is 1 if a
|
|
write caused the exception and otherwise 0'. 'old_set' is the
|
|
signal set which should be restored */
|
|
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
|
|
int is_write, sigset_t *old_set,
|
|
void *puc)
|
|
{
|
|
TranslationBlock *tb;
|
|
int ret;
|
|
|
|
if (cpu_single_env)
|
|
env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
|
#if defined(DEBUG_SIGNAL)
|
|
qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
|
pc, address, is_write, *(unsigned long *)old_set);
|
|
#endif
|
|
/* XXX: locking issue */
|
|
if (is_write && page_unprotect(h2g(address), pc, puc)) {
|
|
return 1;
|
|
}
|
|
|
|
/* see if it is an MMU fault */
|
|
ret = cpu_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
|
|
if (ret < 0)
|
|
return 0; /* not an MMU fault */
|
|
if (ret == 0)
|
|
return 1; /* the MMU fault was handled without causing real CPU fault */
|
|
/* now we have a real cpu fault */
|
|
tb = tb_find_pc(pc);
|
|
if (tb) {
|
|
/* the PC is inside the translated code. It means that we have
|
|
a virtual CPU fault */
|
|
cpu_restore_state(tb, env, pc, puc);
|
|
}
|
|
|
|
/* we restore the process signal mask as the sigreturn should
|
|
do it (XXX: use sigsetjmp) */
|
|
sigprocmask(SIG_SETMASK, old_set, NULL);
|
|
EXCEPTION_ACTION;
|
|
|
|
/* never comes here */
|
|
return 1;
|
|
}
|
|
|
|
#if defined(__i386__)
|
|
|
|
#if defined(__APPLE__)
|
|
# include <sys/ucontext.h>
|
|
|
|
# define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
|
|
# define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
|
|
# define ERROR_sig(context) ((context)->uc_mcontext->es.err)
|
|
# define MASK_sig(context) ((context)->uc_sigmask)
|
|
#elif defined (__NetBSD__)
|
|
# include <ucontext.h>
|
|
|
|
# define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP])
|
|
# define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
|
|
# define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
|
|
# define MASK_sig(context) ((context)->uc_sigmask)
|
|
#elif defined (__FreeBSD__) || defined(__DragonFly__)
|
|
# include <ucontext.h>
|
|
|
|
# define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext.mc_eip))
|
|
# define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
|
|
# define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
|
|
# define MASK_sig(context) ((context)->uc_sigmask)
|
|
#elif defined(__OpenBSD__)
|
|
# define EIP_sig(context) ((context)->sc_eip)
|
|
# define TRAP_sig(context) ((context)->sc_trapno)
|
|
# define ERROR_sig(context) ((context)->sc_err)
|
|
# define MASK_sig(context) ((context)->sc_mask)
|
|
#else
|
|
# define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
|
|
# define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
|
|
# define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
|
|
# define MASK_sig(context) ((context)->uc_sigmask)
|
|
#endif
|
|
|
|
int cpu_signal_handler(int host_signum, void *pinfo,
|
|
void *puc)
|
|
{
|
|
siginfo_t *info = pinfo;
|
|
#if defined(__NetBSD__) || defined (__FreeBSD__) || defined(__DragonFly__)
|
|
ucontext_t *uc = puc;
|
|
#elif defined(__OpenBSD__)
|
|
struct sigcontext *uc = puc;
|
|
#else
|
|
struct ucontext *uc = puc;
|
|
#endif
|
|
unsigned long pc;
|
|
int trapno;
|
|
|
|
#ifndef REG_EIP
|
|
/* for glibc 2.1 */
|
|
#define REG_EIP EIP
|
|
#define REG_ERR ERR
|
|
#define REG_TRAPNO TRAPNO
|
|
#endif
|
|
pc = EIP_sig(uc);
|
|
trapno = TRAP_sig(uc);
|
|
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
trapno == 0xe ?
|
|
(ERROR_sig(uc) >> 1) & 1 : 0,
|
|
&MASK_sig(uc), puc);
|
|
}
|
|
|
|
#elif defined(__x86_64__)
|
|
|
|
#ifdef __NetBSD__
|
|
#define PC_sig(context) _UC_MACHINE_PC(context)
|
|
#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
|
|
#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
|
|
#define MASK_sig(context) ((context)->uc_sigmask)
|
|
#elif defined(__OpenBSD__)
|
|
#define PC_sig(context) ((context)->sc_rip)
|
|
#define TRAP_sig(context) ((context)->sc_trapno)
|
|
#define ERROR_sig(context) ((context)->sc_err)
|
|
#define MASK_sig(context) ((context)->sc_mask)
|
|
#elif defined (__FreeBSD__) || defined(__DragonFly__)
|
|
#include <ucontext.h>
|
|
|
|
#define PC_sig(context) (*((unsigned long*)&(context)->uc_mcontext.mc_rip))
|
|
#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
|
|
#define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
|
|
#define MASK_sig(context) ((context)->uc_sigmask)
|
|
#else
|
|
#define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP])
|
|
#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
|
|
#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
|
|
#define MASK_sig(context) ((context)->uc_sigmask)
|
|
#endif
|
|
|
|
int cpu_signal_handler(int host_signum, void *pinfo,
|
|
void *puc)
|
|
{
|
|
siginfo_t *info = pinfo;
|
|
unsigned long pc;
|
|
#if defined(__NetBSD__) || defined (__FreeBSD__) || defined(__DragonFly__)
|
|
ucontext_t *uc = puc;
|
|
#elif defined(__OpenBSD__)
|
|
struct sigcontext *uc = puc;
|
|
#else
|
|
struct ucontext *uc = puc;
|
|
#endif
|
|
|
|
pc = PC_sig(uc);
|
|
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
TRAP_sig(uc) == 0xe ?
|
|
(ERROR_sig(uc) >> 1) & 1 : 0,
|
|
&MASK_sig(uc), puc);
|
|
}
|
|
|
|
#elif defined(_ARCH_PPC)
|
|
|
|
/***********************************************************************
|
|
* signal context platform-specific definitions
|
|
* From Wine
|
|
*/
|
|
#ifdef linux
|
|
/* All Registers access - only for local access */
|
|
# define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
|
|
/* Gpr Registers access */
|
|
# define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
|
|
# define IAR_sig(context) REG_sig(nip, context) /* Program counter */
|
|
# define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
|
|
# define CTR_sig(context) REG_sig(ctr, context) /* Count register */
|
|
# define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
|
|
# define LR_sig(context) REG_sig(link, context) /* Link register */
|
|
# define CR_sig(context) REG_sig(ccr, context) /* Condition register */
|
|
/* Float Registers access */
|
|
# define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
|
|
# define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
|
|
/* Exception Registers access */
|
|
# define DAR_sig(context) REG_sig(dar, context)
|
|
# define DSISR_sig(context) REG_sig(dsisr, context)
|
|
# define TRAP_sig(context) REG_sig(trap, context)
|
|
#endif /* linux */
|
|
|
|
#ifdef __APPLE__
|
|
# include <sys/ucontext.h>
|
|
typedef struct ucontext SIGCONTEXT;
|
|
/* All Registers access - only for local access */
|
|
# define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
|
|
# define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
|
|
# define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
|
|
# define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
|
|
/* Gpr Registers access */
|
|
# define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
|
|
# define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
|
|
# define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
|
|
# define CTR_sig(context) REG_sig(ctr, context)
|
|
# define XER_sig(context) REG_sig(xer, context) /* Link register */
|
|
# define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
|
|
# define CR_sig(context) REG_sig(cr, context) /* Condition register */
|
|
/* Float Registers access */
|
|
# define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
|
|
# define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
|
|
/* Exception Registers access */
|
|
# define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
|
|
# define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
|
|
# define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
|
|
#endif /* __APPLE__ */
|
|
|
|
int cpu_signal_handler(int host_signum, void *pinfo,
|
|
void *puc)
|
|
{
|
|
siginfo_t *info = pinfo;
|
|
struct ucontext *uc = puc;
|
|
unsigned long pc;
|
|
int is_write;
|
|
|
|
pc = IAR_sig(uc);
|
|
is_write = 0;
|
|
#if 0
|
|
/* ppc 4xx case */
|
|
if (DSISR_sig(uc) & 0x00800000)
|
|
is_write = 1;
|
|
#else
|
|
if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
|
|
is_write = 1;
|
|
#endif
|
|
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
is_write, &uc->uc_sigmask, puc);
|
|
}
|
|
|
|
#elif defined(__alpha__)
|
|
|
|
int cpu_signal_handler(int host_signum, void *pinfo,
|
|
void *puc)
|
|
{
|
|
siginfo_t *info = pinfo;
|
|
struct ucontext *uc = puc;
|
|
uint32_t *pc = uc->uc_mcontext.sc_pc;
|
|
uint32_t insn = *pc;
|
|
int is_write = 0;
|
|
|
|
/* XXX: need kernel patch to get write flag faster */
|
|
switch (insn >> 26) {
|
|
case 0x0d: // stw
|
|
case 0x0e: // stb
|
|
case 0x0f: // stq_u
|
|
case 0x24: // stf
|
|
case 0x25: // stg
|
|
case 0x26: // sts
|
|
case 0x27: // stt
|
|
case 0x2c: // stl
|
|
case 0x2d: // stq
|
|
case 0x2e: // stl_c
|
|
case 0x2f: // stq_c
|
|
is_write = 1;
|
|
}
|
|
|
|
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
is_write, &uc->uc_sigmask, puc);
|
|
}
|
|
#elif defined(__sparc__)
|
|
|
|
int cpu_signal_handler(int host_signum, void *pinfo,
|
|
void *puc)
|
|
{
|
|
siginfo_t *info = pinfo;
|
|
int is_write;
|
|
uint32_t insn;
|
|
#if !defined(__arch64__) || defined(CONFIG_SOLARIS)
|
|
uint32_t *regs = (uint32_t *)(info + 1);
|
|
void *sigmask = (regs + 20);
|
|
/* XXX: is there a standard glibc define ? */
|
|
unsigned long pc = regs[1];
|
|
#else
|
|
#ifdef __linux__
|
|
struct sigcontext *sc = puc;
|
|
unsigned long pc = sc->sigc_regs.tpc;
|
|
void *sigmask = (void *)sc->sigc_mask;
|
|
#elif defined(__OpenBSD__)
|
|
struct sigcontext *uc = puc;
|
|
unsigned long pc = uc->sc_pc;
|
|
void *sigmask = (void *)(long)uc->sc_mask;
|
|
#endif
|
|
#endif
|
|
|
|
/* XXX: need kernel patch to get write flag faster */
|
|
is_write = 0;
|
|
insn = *(uint32_t *)pc;
|
|
if ((insn >> 30) == 3) {
|
|
switch((insn >> 19) & 0x3f) {
|
|
case 0x05: // stb
|
|
case 0x15: // stba
|
|
case 0x06: // sth
|
|
case 0x16: // stha
|
|
case 0x04: // st
|
|
case 0x14: // sta
|
|
case 0x07: // std
|
|
case 0x17: // stda
|
|
case 0x0e: // stx
|
|
case 0x1e: // stxa
|
|
case 0x24: // stf
|
|
case 0x34: // stfa
|
|
case 0x27: // stdf
|
|
case 0x37: // stdfa
|
|
case 0x26: // stqf
|
|
case 0x36: // stqfa
|
|
case 0x25: // stfsr
|
|
case 0x3c: // casa
|
|
case 0x3e: // casxa
|
|
is_write = 1;
|
|
break;
|
|
}
|
|
}
|
|
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
is_write, sigmask, NULL);
|
|
}
|
|
|
|
#elif defined(__arm__)
|
|
|
|
int cpu_signal_handler(int host_signum, void *pinfo,
|
|
void *puc)
|
|
{
|
|
siginfo_t *info = pinfo;
|
|
struct ucontext *uc = puc;
|
|
unsigned long pc;
|
|
int is_write;
|
|
|
|
#if (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
|
|
pc = uc->uc_mcontext.gregs[R15];
|
|
#else
|
|
pc = uc->uc_mcontext.arm_pc;
|
|
#endif
|
|
/* XXX: compute is_write */
|
|
is_write = 0;
|
|
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
is_write,
|
|
&uc->uc_sigmask, puc);
|
|
}
|
|
|
|
#elif defined(__mc68000)
|
|
|
|
int cpu_signal_handler(int host_signum, void *pinfo,
|
|
void *puc)
|
|
{
|
|
siginfo_t *info = pinfo;
|
|
struct ucontext *uc = puc;
|
|
unsigned long pc;
|
|
int is_write;
|
|
|
|
pc = uc->uc_mcontext.gregs[16];
|
|
/* XXX: compute is_write */
|
|
is_write = 0;
|
|
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
is_write,
|
|
&uc->uc_sigmask, puc);
|
|
}
|
|
|
|
#elif defined(__ia64)
|
|
|
|
#ifndef __ISR_VALID
|
|
/* This ought to be in <bits/siginfo.h>... */
|
|
# define __ISR_VALID 1
|
|
#endif
|
|
|
|
int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
|
|
{
|
|
siginfo_t *info = pinfo;
|
|
struct ucontext *uc = puc;
|
|
unsigned long ip;
|
|
int is_write = 0;
|
|
|
|
ip = uc->uc_mcontext.sc_ip;
|
|
switch (host_signum) {
|
|
case SIGILL:
|
|
case SIGFPE:
|
|
case SIGSEGV:
|
|
case SIGBUS:
|
|
case SIGTRAP:
|
|
if (info->si_code && (info->si_segvflags & __ISR_VALID))
|
|
/* ISR.W (write-access) is bit 33: */
|
|
is_write = (info->si_isr >> 33) & 1;
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
return handle_cpu_signal(ip, (unsigned long)info->si_addr,
|
|
is_write,
|
|
&uc->uc_sigmask, puc);
|
|
}
|
|
|
|
#elif defined(__s390__)
|
|
|
|
int cpu_signal_handler(int host_signum, void *pinfo,
|
|
void *puc)
|
|
{
|
|
siginfo_t *info = pinfo;
|
|
struct ucontext *uc = puc;
|
|
unsigned long pc;
|
|
int is_write;
|
|
|
|
pc = uc->uc_mcontext.psw.addr;
|
|
/* XXX: compute is_write */
|
|
is_write = 0;
|
|
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
is_write, &uc->uc_sigmask, puc);
|
|
}
|
|
|
|
#elif defined(__mips__)
|
|
|
|
int cpu_signal_handler(int host_signum, void *pinfo,
|
|
void *puc)
|
|
{
|
|
siginfo_t *info = pinfo;
|
|
struct ucontext *uc = puc;
|
|
greg_t pc = uc->uc_mcontext.pc;
|
|
int is_write;
|
|
|
|
/* XXX: compute is_write */
|
|
is_write = 0;
|
|
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
is_write, &uc->uc_sigmask, puc);
|
|
}
|
|
|
|
#elif defined(__hppa__)
|
|
|
|
int cpu_signal_handler(int host_signum, void *pinfo,
|
|
void *puc)
|
|
{
|
|
struct siginfo *info = pinfo;
|
|
struct ucontext *uc = puc;
|
|
unsigned long pc;
|
|
int is_write;
|
|
|
|
pc = uc->uc_mcontext.sc_iaoq[0];
|
|
/* FIXME: compute is_write */
|
|
is_write = 0;
|
|
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
is_write,
|
|
&uc->uc_sigmask, puc);
|
|
}
|
|
|
|
#else
|
|
|
|
#error host CPU specific signal handler needed
|
|
|
|
#endif
|
|
|
|
#endif /* !defined(CONFIG_SOFTMMU) */
|