5aeb368966
The SSE-200 has a CPU_IDENTITY register block, which is a set of read-only registers. As well as the usual PID/CID registers, there is a single CPUID register which indicates whether the CPU is CPU 0 or CPU 1. Implement a model of this register block. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-20-peter.maydell@linaro.org |
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macio | ||
a9scu.c | ||
applesmc.c | ||
arm11scu.c | ||
arm_integrator_debug.c | ||
arm_l2x0.c | ||
arm_sysctl.c | ||
armsse-cpuid.c | ||
aspeed_scu.c | ||
aspeed_sdmc.c | ||
auxbus.c | ||
bcm2835_mbox.c | ||
bcm2835_property.c | ||
bcm2835_rng.c | ||
cbus.c | ||
debugexit.c | ||
eccmemctl.c | ||
edu.c | ||
exynos4210_clk.c | ||
exynos4210_pmu.c | ||
exynos4210_rng.c | ||
imx2_wdt.c | ||
imx6_ccm.c | ||
imx6_src.c | ||
imx6ul_ccm.c | ||
imx7_ccm.c | ||
imx7_gpr.c | ||
imx7_snvs.c | ||
imx25_ccm.c | ||
imx31_ccm.c | ||
imx_ccm.c | ||
iotkit-secctl.c | ||
iotkit-sysctl.c | ||
iotkit-sysinfo.c | ||
ivshmem.c | ||
Makefile.objs | ||
max111x.c | ||
milkymist-hpdmc.c | ||
milkymist-pfpu.c | ||
mips_cmgcr.c | ||
mips_cpc.c | ||
mips_itu.c | ||
mos6522.c | ||
mps2-fpgaio.c | ||
mps2-scc.c | ||
msf2-sysreg.c | ||
mst_fpga.c | ||
nrf51_rng.c | ||
omap_clk.c | ||
omap_gpmc.c | ||
omap_l4.c | ||
omap_sdrc.c | ||
omap_tap.c | ||
pc-testdev.c | ||
pca9552.c | ||
pci-testdev.c | ||
puv3_pm.c | ||
pvpanic.c | ||
sga.c | ||
slavio_misc.c | ||
stm32f2xx_syscfg.c | ||
tmp105.c | ||
tmp105.h | ||
tmp421.c | ||
trace-events | ||
tz-mpc.c | ||
tz-msc.c | ||
tz-ppc.c | ||
unimp.c | ||
vmcoreinfo.c | ||
zynq_slcr.c | ||
zynq-xadc.c |