75750e4d43
The Arm IoTKit includes a system control element which provides a block of read-only ID registers and a block of read-write control registers. Implement a minimal version of this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180820141116.9118-9-peter.maydell@linaro.org
262 lines
7.4 KiB
C
262 lines
7.4 KiB
C
/*
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* ARM IoTKit system control element
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*
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* Copyright (c) 2018 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/*
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* This is a model of the "system control element" which is part of the
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* Arm IoTKit and documented in
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* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
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* Specifically, it implements the "system control register" blocks.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "trace.h"
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#include "qapi/error.h"
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#include "sysemu/sysemu.h"
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#include "hw/sysbus.h"
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#include "hw/registerfields.h"
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#include "hw/misc/iotkit-sysctl.h"
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REG32(SECDBGSTAT, 0x0)
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REG32(SECDBGSET, 0x4)
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REG32(SECDBGCLR, 0x8)
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REG32(RESET_SYNDROME, 0x100)
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REG32(RESET_MASK, 0x104)
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REG32(SWRESET, 0x108)
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FIELD(SWRESET, SWRESETREQ, 9, 1)
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REG32(GRETREG, 0x10c)
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REG32(INITSVRTOR0, 0x110)
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REG32(CPUWAIT, 0x118)
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REG32(BUSWAIT, 0x11c)
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REG32(WICCTRL, 0x120)
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REG32(PID4, 0xfd0)
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REG32(PID5, 0xfd4)
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REG32(PID6, 0xfd8)
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REG32(PID7, 0xfdc)
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REG32(PID0, 0xfe0)
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REG32(PID1, 0xfe4)
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REG32(PID2, 0xfe8)
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REG32(PID3, 0xfec)
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REG32(CID0, 0xff0)
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REG32(CID1, 0xff4)
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REG32(CID2, 0xff8)
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REG32(CID3, 0xffc)
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/* PID/CID values */
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static const int sysctl_id[] = {
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0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
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0x54, 0xb8, 0x0b, 0x00, /* PID0..PID3 */
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0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
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};
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static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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IoTKitSysCtl *s = IOTKIT_SYSCTL(opaque);
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uint64_t r;
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switch (offset) {
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case A_SECDBGSTAT:
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r = s->secure_debug;
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break;
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case A_RESET_SYNDROME:
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r = s->reset_syndrome;
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break;
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case A_RESET_MASK:
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r = s->reset_mask;
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break;
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case A_GRETREG:
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r = s->gretreg;
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break;
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case A_INITSVRTOR0:
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r = s->initsvrtor0;
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break;
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case A_CPUWAIT:
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r = s->cpuwait;
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break;
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case A_BUSWAIT:
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/* In IoTKit BUSWAIT is reserved, R/O, zero */
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r = 0;
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break;
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case A_WICCTRL:
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r = s->wicctrl;
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break;
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case A_PID4 ... A_CID3:
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r = sysctl_id[(offset - A_PID4) / 4];
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break;
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case A_SECDBGSET:
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case A_SECDBGCLR:
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case A_SWRESET:
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qemu_log_mask(LOG_GUEST_ERROR,
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"IoTKit SysCtl read: read of WO offset %x\n",
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(int)offset);
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r = 0;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"IoTKit SysCtl read: bad offset %x\n", (int)offset);
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r = 0;
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break;
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}
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trace_iotkit_sysctl_read(offset, r, size);
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return r;
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}
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static void iotkit_sysctl_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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IoTKitSysCtl *s = IOTKIT_SYSCTL(opaque);
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trace_iotkit_sysctl_write(offset, value, size);
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/*
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* Most of the state here has to do with control of reset and
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* similar kinds of power up -- for instance the guest can ask
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* what the reason for the last reset was, or forbid reset for
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* some causes (like the non-secure watchdog). Most of this is
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* not relevant to QEMU, which doesn't really model anything other
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* than a full power-on reset.
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* We just model the registers as reads-as-written.
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*/
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switch (offset) {
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case A_RESET_SYNDROME:
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qemu_log_mask(LOG_UNIMP,
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"IoTKit SysCtl RESET_SYNDROME unimplemented\n");
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s->reset_syndrome = value;
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break;
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case A_RESET_MASK:
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qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl RESET_MASK unimplemented\n");
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s->reset_mask = value;
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break;
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case A_GRETREG:
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/*
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* General retention register, which is only reset by a power-on
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* reset. Technically this implementation is complete, since
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* QEMU only supports power-on resets...
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*/
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s->gretreg = value;
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break;
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case A_INITSVRTOR0:
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qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVRTOR0 unimplemented\n");
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s->initsvrtor0 = value;
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break;
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case A_CPUWAIT:
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qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CPUWAIT unimplemented\n");
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s->cpuwait = value;
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break;
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case A_WICCTRL:
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qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl WICCTRL unimplemented\n");
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s->wicctrl = value;
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break;
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case A_SECDBGSET:
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/* write-1-to-set */
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qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SECDBGSET unimplemented\n");
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s->secure_debug |= value;
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break;
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case A_SECDBGCLR:
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/* write-1-to-clear */
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s->secure_debug &= ~value;
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break;
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case A_SWRESET:
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/* One w/o bit to request a reset; all other bits reserved */
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if (value & R_SWRESET_SWRESETREQ_MASK) {
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qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
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}
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break;
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case A_BUSWAIT: /* In IoTKit BUSWAIT is reserved, R/O, zero */
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case A_SECDBGSTAT:
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case A_PID4 ... A_CID3:
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qemu_log_mask(LOG_GUEST_ERROR,
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"IoTKit SysCtl write: write of RO offset %x\n",
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(int)offset);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"IoTKit SysCtl write: bad offset %x\n", (int)offset);
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break;
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}
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}
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static const MemoryRegionOps iotkit_sysctl_ops = {
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.read = iotkit_sysctl_read,
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.write = iotkit_sysctl_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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/* byte/halfword accesses are just zero-padded on reads and writes */
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.impl.min_access_size = 4,
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.impl.max_access_size = 4,
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.valid.min_access_size = 1,
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.valid.max_access_size = 4,
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};
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static void iotkit_sysctl_reset(DeviceState *dev)
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{
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IoTKitSysCtl *s = IOTKIT_SYSCTL(dev);
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trace_iotkit_sysctl_reset();
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s->secure_debug = 0;
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s->reset_syndrome = 1;
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s->reset_mask = 0;
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s->gretreg = 0;
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s->initsvrtor0 = 0x10000000;
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s->cpuwait = 0;
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s->wicctrl = 0;
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}
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static void iotkit_sysctl_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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IoTKitSysCtl *s = IOTKIT_SYSCTL(obj);
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memory_region_init_io(&s->iomem, obj, &iotkit_sysctl_ops,
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s, "iotkit-sysctl", 0x1000);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static const VMStateDescription iotkit_sysctl_vmstate = {
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.name = "iotkit-sysctl",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(secure_debug, IoTKitSysCtl),
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VMSTATE_UINT32(reset_syndrome, IoTKitSysCtl),
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VMSTATE_UINT32(reset_mask, IoTKitSysCtl),
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VMSTATE_UINT32(gretreg, IoTKitSysCtl),
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VMSTATE_UINT32(initsvrtor0, IoTKitSysCtl),
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VMSTATE_UINT32(cpuwait, IoTKitSysCtl),
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VMSTATE_UINT32(wicctrl, IoTKitSysCtl),
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VMSTATE_END_OF_LIST()
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}
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};
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static void iotkit_sysctl_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->vmsd = &iotkit_sysctl_vmstate;
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dc->reset = iotkit_sysctl_reset;
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}
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static const TypeInfo iotkit_sysctl_info = {
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.name = TYPE_IOTKIT_SYSCTL,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(IoTKitSysCtl),
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.instance_init = iotkit_sysctl_init,
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.class_init = iotkit_sysctl_class_init,
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};
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static void iotkit_sysctl_register_types(void)
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{
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type_register_static(&iotkit_sysctl_info);
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}
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type_init(iotkit_sysctl_register_types);
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