Peter Maydell 436c0cbbeb target/arm/cpu: Give Cortex-A15 and -A7 the EL2 feature ... The Cortex-A15 and Cortex-A7 both have EL2; now we've implemented it properly we can enable the feature bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20181109173553.22341-3-peter.maydell@linaro.org		2018-11-13 10:47:59 +00:00
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alpha	target/alpha: remove tlb_flush from alpha_cpu_initfn	2018-10-18 18:58:10 -07:00
arm	target/arm/cpu: Give Cortex-A15 and -A7 the EL2 feature	2018-11-13 10:47:59 +00:00
cris	target/cris/translate: Get rid of qemu_log_separate()	2018-10-16 17:57:23 +02:00
hppa	target/hppa: Raise exception 26 on emulated hardware	2018-10-16 15:32:22 -07:00
i386	target/i386: Clear RF on SYSCALL instruction	2018-11-06 21:35:05 +01:00
lm32
m68k	target/m68k: use EXCP_ILLEGAL instead of EXCP_UNSUPPORTED	2018-11-01 12:12:24 +01:00
microblaze
mips	target/mips: Amend MXU ASE overview note	2018-10-29 14:13:59 +01:00
moxie
nios2
openrisc	decodetree: Remove "insn" argument from trans_* expanders	2018-10-31 16:48:54 +00:00
ppc	ppc/spapr_caps: Add SPAPR_CAP_NESTED_KVM_HV	2018-11-08 13:08:35 +11:00
riscv	target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64	2018-10-30 11:04:28 -07:00
s390x	target/s390x: Check HAVE_ATOMIC128 and HAVE_CMPXCHG128 at translate	2018-10-18 19:46:53 -07:00
sh4
sparc
tilegx
tricore
unicore32	target/unicore32: remove tlb_flush from uc32_init_fn	2018-10-18 18:58:10 -07:00
xtensa	target/xtensa: extract gen_check_interrupts call	2018-10-01 11:08:36 -07:00