qemu-e2k/target/riscv
Steve Sistare aeaafb1e59 migration: export migration_is_running
Delete the MigrationState parameter from migration_is_running and move
it to the public API in misc.h.

Signed-off-by: Steve Sistare <steven.sistare@oracle.com>
Link: https://lore.kernel.org/r/1710179338-294359-5-git-send-email-steven.sistare@oracle.com
Signed-off-by: Peter Xu <peterx@redhat.com>
2024-03-11 16:28:59 -04:00
..
insn_trans trans_rvv.c.inc: remove 'is_store' bool from load/store fns 2024-03-08 20:48:03 +10:00
kvm migration: export migration_is_running 2024-03-11 16:28:59 -04:00
tcg target/riscv: Promote svade to a normal extension 2024-03-08 16:35:28 +10:00
arch_dump.c
bitmanip_helper.c
common-semi-target.h
cpu_bits.h target/riscv: FCSR doesn't contain vxrm and vxsat 2024-02-09 20:43:14 +10:00
cpu_cfg.h RISC-V: Add support for Ztso 2024-03-08 19:47:48 +10:00
cpu_helper.c target/riscv: Fix privilege mode of G-stage translation for debugging 2024-03-08 20:48:03 +10:00
cpu_user.h
cpu_vendorid.h
cpu-param.h
cpu-qom.h target/riscv: add rv32i, rv32e and rv64e CPUs 2024-02-09 20:49:41 +10:00
cpu.c target/riscv: move ratified/frozen exts to non-experimental 2024-03-08 20:48:03 +10:00
cpu.h target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit 2024-03-08 20:48:03 +10:00
crypto_helper.c
csr.c target/riscv: UPDATE xATP write CSR 2024-03-08 16:38:09 +10:00
debug.c target/riscv: Implement optional CSR mcontext of debug Sdtrig extension 2024-02-09 20:40:32 +10:00
debug.h
fpu_helper.c
gdbstub.c gdbstub: Add members to identify registers to GDBFeature 2024-02-28 09:10:11 +00:00
helper.h
insn16.decode
insn32.decode
instmap.h
internals.h
Kconfig kconfig: use "select" to enable semihosting 2024-02-09 17:52:30 +00:00
m128_helper.c
machine.c target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit 2024-03-08 20:48:03 +10:00
meson.build
monitor.c
op_helper.c target/riscv: Replace cpu_mmu_index with riscv_env_mmu_index 2024-02-03 16:46:10 +10:00
pmp.c target/riscv: pmp: Ignore writes when RW=01 and MML=0 2024-01-10 18:47:47 +10:00
pmp.h
pmu.c
pmu.h target/riscv: Add missing include guard in pmu.h 2024-03-08 16:39:32 +10:00
riscv-qmp-cmds.c riscv-qmp-cmds.c: add profile flags in cpu-model-expansion 2024-01-10 18:47:47 +10:00
sbi_ecall_interface.h
time_helper.c
time_helper.h
trace-events
trace.h
translate.c RISC-V: Add support for Ztso 2024-03-08 19:47:48 +10:00
vcrypto_helper.c
vector_helper.c target/riscv: Fix shift count overflow 2024-03-08 20:48:03 +10:00
vector_internals.c riscv: Clean up includes 2024-01-30 21:20:20 +03:00
vector_internals.h riscv: Clean up includes 2024-01-30 21:20:20 +03:00
xthead.decode
XVentanaCondOps.decode
zce_helper.c