qemu-e2k/target-arm
Peter Maydell d6be29e3fb target-arm: handle address translations that start at level 3
The ARMv8 address translation system defines that a page table walk
starts at a level which depends on the translation granule size
and the number of bits of virtual address that need to be resolved.
Where the translation granule is 64KB and the guest sets the
TCR.TxSZ field to between 35 and 39, it's actually possible to
start at level 3 (the final level). QEMU's implementation failed
to handle this case, and so we would set level to 2 and behave
incorrectly (including invoking the C undefined behaviour of
shifting left by a negative number). Correct the code that
determines the starting level to deal with the start-at-3 case,
by replacing the if-else ladder with an expression derived from
the ARM ARM pseudocode version.

This error was detected by the Coverity scan, which spotted
the potential shift by a negative number.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1415890569-7454-1-git-send-email-peter.maydell@linaro.org
2014-11-17 19:30:28 +00:00
..
Makefile.objs target-arm: add emulation of PSCI calls for system emulation 2014-10-24 12:19:13 +01:00
arm-semi.c cpu: Move opaque field from CPU_COMMON to CPUState 2014-03-13 19:20:47 +01:00
arm_ldst.h softmmu: introduce cpu_ldst.h 2014-06-05 16:10:33 +02:00
cpu-qom.h target-arm: add emulation of PSCI calls for system emulation 2014-10-24 12:19:13 +01:00
cpu.c target-arm: Separate out M profile cpu_exec_interrupt handling 2014-11-04 12:05:23 +00:00
cpu.h target-arm: Correct condition for taking VIRQ and VFIQ 2014-11-04 12:05:23 +00:00
cpu64.c target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any" 2014-10-24 12:19:13 +01:00
crypto_helper.c target-arm: Use Common Tables in AES Instructions 2014-06-16 13:24:33 +02:00
gdbstub.c cpu: Introduce CPUClass::gdb_{read,write}_register() 2013-07-27 00:04:17 +02:00
gdbstub64.c target-arm/gdbstub64.c: remove useless 'break' statement. 2014-04-17 21:34:06 +01:00
helper-a64.c target-arm: rename arm_current_pl to arm_current_el 2014-10-24 12:19:14 +01:00
helper-a64.h target-arm: A64: Implement CRC instructions 2014-06-09 16:06:12 +01:00
helper.c target-arm: handle address translations that start at level 3 2014-11-17 19:30:28 +00:00
helper.h target-arm: A64: Emulate the SMC insn 2014-09-29 18:48:50 +01:00
internals.h target-arm: rename arm_current_pl to arm_current_el 2014-10-24 12:19:14 +01:00
iwmmxt_helper.c target-arm: Delete unused iwmmxt_msadb helper 2014-06-09 16:06:12 +01:00
kvm-consts.h target-arm: add missing PSCI constants needed for PSCI emulation 2014-10-24 12:19:12 +01:00
kvm-stub.c target-arm: Initialize cpreg list from KVM when using KVM 2013-06-25 18:16:10 +01:00
kvm.c target-arm: Common kvm_arm_vcpu_init() for KVM ARM and KVM ARM64 2014-06-19 18:33:02 +01:00
kvm32.c target-arm: Implement vCPU reset via KVM_ARM_VCPU_INIT for 32-bit CPUs 2014-07-08 13:05:11 +01:00
kvm64.c target-arm: A64: Break out aarch64_save/restore_sp 2014-08-04 14:41:54 +01:00
kvm_arm.h target-arm: Common kvm_arm_vcpu_init() for KVM ARM and KVM ARM64 2014-06-19 18:33:02 +01:00
machine.c target-arm: increase arrays of registers R13 & R14 2014-10-24 12:19:14 +01:00
neon_helper.c target-arm: add support for v8 VMULL.P64 instruction 2014-06-09 16:06:11 +01:00
op_addsub.h Correct spelling of licensed 2011-07-23 11:26:12 -05:00
op_helper.c target-arm: A32: Emulate the SMC instruction 2014-10-24 12:19:15 +01:00
psci.c target-arm: add emulation of PSCI calls for system emulation 2014-10-24 12:19:13 +01:00
translate-a64.c target-arm: A64: remove redundant store 2014-11-02 10:04:34 +03:00
translate.c target-arm/translate.c: Don't pass CPUARMState * to disas_arm_insn() 2014-11-04 12:05:11 +00:00
translate.h target-arm: rename arm_current_pl to arm_current_el 2014-10-24 12:19:14 +01:00