qemu-e2k/target/riscv
Conor Dooley 48249c023d target/riscv: fix invalid riscv,event-to-mhpmcounters entry
dt-validate complains:
> soc: pmu: {'riscv,event-to-mhpmcounters':
> [[1, 1, 524281], [2, 2, 524284], [65561, 65561, 524280],
> [65563, 65563, 524280], [65569, 65569, 524280], [0, 0, 0], [0, 0]],
> pmu: riscv,event-to-mhpmcounters:6: [0, 0] is too short

There are bogus 0 entries added at the end, of which one is of
insufficient length. This happens because only 15 of
fdt_event_ctr_map[]'s 20 elements are populated & qemu_fdt_setprop() is
called using the size of the array.
Reduce the array to 15 elements to make the error go away.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230404173333.35179-1-conor@kernel.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05 10:49:50 +10:00
..
insn_trans target/riscv: redirect XVentanaCondOps to use the Zicond functions 2023-05-05 10:49:50 +10:00
arch_dump.c
bitmanip_helper.c
common-semi-target.h
cpu_bits.h target/riscv: Add csr support for svadu 2023-03-01 17:28:15 -08:00
cpu_helper.c target/riscv: Simplify type conversion for CPURISCVState 2023-05-05 10:49:49 +10:00
cpu_user.h
cpu_vendorid.h RISC-V: Add initial support for T-Head C906 2023-02-07 08:19:23 +10:00
cpu-param.h target/riscv: Remove NB_MMU_MODES define 2023-03-13 06:44:37 -07:00
cpu.c target/riscv: Simplify type conversion for CPURISCVState 2023-05-05 10:49:49 +10:00
cpu.h target/riscv: Simplify type conversion for CPURISCVState 2023-05-05 10:49:49 +10:00
crypto_helper.c
csr.c target/riscv: Simplify arguments for riscv_csrrw_check 2023-05-05 10:49:49 +10:00
debug.c target/riscv: set tval for triggered watchpoints 2023-02-07 08:19:23 +10:00
debug.h
fpu_helper.c target/riscv: Remove helper_set_rod_rounding_mode 2023-01-20 10:14:14 +10:00
gdbstub.c target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig 2023-05-05 10:49:49 +10:00
helper.h target/riscv: implement Zicbom extension 2023-03-05 11:49:42 -08:00
insn16.decode
insn32.decode target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder 2023-03-05 11:49:43 -08:00
instmap.h
internals.h
Kconfig
kvm_riscv.h
kvm-stub.c
kvm.c target/riscv: fix SBI getchar handler for KVM 2023-02-07 08:19:23 +10:00
m128_helper.c
machine.c target/riscv/cpu: remove CPUArchState::features and friends 2023-03-01 13:47:16 -08:00
meson.build RISC-V: Adding XTheadCmo ISA extension 2023-02-07 08:19:23 +10:00
monitor.c target/riscv: remove RISCV_FEATURE_MMU 2023-03-01 13:47:15 -08:00
op_helper.c target/riscv: implement Zicbom extension 2023-03-05 11:49:42 -08:00
pmp.c target/riscv: remove RISCV_FEATURE_MMU 2023-03-01 13:47:15 -08:00
pmp.h
pmu.c target/riscv: fix invalid riscv,event-to-mhpmcounters entry 2023-05-05 10:49:50 +10:00
pmu.h riscv: Clean up includes 2023-02-08 07:28:05 +01:00
sbi_ecall_interface.h
time_helper.c target/riscv: Simplify type conversion for CPURISCVState 2023-05-05 10:49:49 +10:00
time_helper.h target/riscv: Simplify type conversion for CPURISCVState 2023-05-05 10:49:49 +10:00
trace-events
trace.h
translate.c Sixth RISC-V PR for 8.0 2023-03-07 12:53:00 +00:00
vector_helper.c target/riscv/vector_helper.c: avoid env_archcpu() when reading RISCVCPUConfig 2023-03-01 18:09:45 -08:00
xthead.decode RISC-V: Adding XTheadFmv ISA extension 2023-02-07 08:19:23 +10:00
XVentanaCondOps.decode