Philippe Mathieu-Daudé de6cd7599b meson: Replace softmmu_ss -> system_ss ... We use the user_ss[] array to hold the user emulation sources, and the softmmu_ss[] array to hold the system emulation ones. Hold the latter in the 'system_ss[]' array for parity with user emulation. Mechanical change doing: $ sed -i -e s/softmmu_ss/system_ss/g $(git grep -l softmmu_ss) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230613133347.82210-10-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>		2023-06-20 10:01:30 +02:00
..
insn_trans	target/riscv: Enable PC-relative translation	2023-06-13 17:37:12 +10:00
arch_dump.c	target/riscv: Fix format for comments	2023-05-05 10:49:50 +10:00
bitmanip_helper.c
common-semi-target.h
cpu_bits.h	riscv: Make sure an exception is raised if a pte is malformed	2023-05-05 10:49:50 +10:00
cpu_cfg.h	target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.h	2023-06-13 17:26:45 +10:00
cpu_helper.c	target/riscv: Fix initialized value for cur_pmmask	2023-06-13 17:42:50 +10:00
cpu_user.h
cpu_vendorid.h	target/riscv: add Ventana's Veyron V1 CPU	2023-05-05 10:49:50 +10:00
cpu-param.h
cpu-qom.h	target/riscv: add Ventana's Veyron V1 CPU	2023-05-05 10:49:50 +10:00
cpu.c	target/riscv: Enable PC-relative translation	2023-06-13 17:37:12 +10:00
cpu.h	target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.h	2023-06-13 17:26:45 +10:00
crypto_helper.c
csr.c	target/riscv: smstateen check for fcsr	2023-06-13 17:23:04 +10:00
debug.c	target/riscv: Fix lines with over 80 characters	2023-05-05 10:49:50 +10:00
debug.h
fpu_helper.c
gdbstub.c	target/riscv: Use PRV_RESERVED instead of PRV_H	2023-05-05 10:49:50 +10:00
helper.h	target/riscv: Handle HLV, HSV via helpers	2023-05-05 10:49:50 +10:00
insn16.decode
insn32.decode
instmap.h
internals.h	target/riscv: Introduce mmuidx_2stage	2023-05-05 10:49:50 +10:00
Kconfig
kvm_riscv.h
kvm-stub.c
kvm.c
m128_helper.c
machine.c
meson.build	meson: Replace softmmu_ss -> system_ss	2023-06-20 10:01:30 +02:00
monitor.c
op_helper.c	target/riscv: Check SUM in the correct register	2023-05-05 10:49:50 +10:00
pmp.c	target/riscv: Smepmp: Return error when access permission not allowed in PMP	2023-06-13 17:45:30 +10:00
pmp.h	target/riscv: Change the return type of pmp_hart_has_privs() to bool	2023-06-13 17:09:13 +10:00
pmu.c	target/riscv: Fix lines with over 80 characters	2023-05-05 10:49:50 +10:00
pmu.h
riscv-qmp-cmds.c	target/riscv: add TYPE_RISCV_DYNAMIC_CPU	2023-05-05 10:49:50 +10:00
sbi_ecall_interface.h	target/riscv: Fix format for comments	2023-05-05 10:49:50 +10:00
time_helper.c
time_helper.h
trace-events
trace.h
translate.c	target/riscv: Remove pc_succ_insn from DisasContext	2023-06-13 17:38:08 +10:00
vector_helper.c	target/riscv/vector_helper.c: Remove the check for extra tail elements	2023-06-13 17:44:41 +10:00
xthead.decode
XVentanaCondOps.decode
zce_helper.c