Frank Chang ae000c5f65 hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer ... Real PDMA doesn't set Control.error if there are 0 bytes to be transferred. The DMA transfer is still success. The following result is PDMA tested in U-Boot on Unmatched board: => mw.l 0x3000000 0x0 <= Disclaim channel 0 => mw.l 0x3000000 0x1 <= Claim channel 0 => mw.l 0x3000004 0x55000000 <= wsize = rsize = 5 (2^5 = 32 bytes) => mw.q 0x3000008 0x0 <= NextBytes = 0 => mw.q 0x3000010 0x84000000 <= NextDestination = 0x84000000 => mw.q 0x3000018 0x84001000 <= NextSource = 0x84001000 => mw.l 0x84000000 0x87654321 <= Fill test data to dst => mw.l 0x84001000 0x12345678 <= Fill test data to src => md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents 84000000: 87654321 !Ce. 84001000: 12345678 xV4. => md.l 0x3000000 8 <= Dump PDMA status 03000000: 00000001 55000000 00000000 00000000 .......U........ 03000010: 84000000 00000000 84001000 00000000 ................ => mw.l 0x3000000 0x3 <= Set channel 0 run and claim bits => md.l 0x3000000 8 <= Dump PDMA status 03000000: 40000001 55000000 00000000 00000000 ...@...U........ 03000010: 84000000 00000000 84001000 00000000 ................ => md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents 84000000: 87654321 !Ce. 84001000: 12345678 xV4. Signed-off-by: Frank Chang <frank.chang@sifive.com> Tested-by: Max Hsu <max.hsu@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210912130553.179501-5-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-09-21 07:56:49 +10:00
..
bcm2835_dma.c
etraxfs_dma.c
i8257.c
i82374.c
Kconfig	hw/dma: Implement a Xilinx CSU DMA model	2021-03-08 17:20:04 +00:00
meson.build	Drop the deprecated unicore32 target	2021-05-12 18:20:52 +02:00
omap_dma.c
pl080.c	Do not include exec/address-spaces.h if it's not really necessary	2021-05-02 17:24:51 +02:00
pl330.c	hw/dma/pl330: Add memory region to replace default	2021-08-25 10:48:50 +01:00
pxa2xx_dma.c	hw/arm: Constify VMStateDescription	2021-05-02 17:24:50 +02:00
rc4030.c
sifive_pdma.c	hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer	2021-09-21 07:56:49 +10:00
soc_dma.c
sparc32_dma.c
trace-events	docs: fix references to docs/devel/tracing.rst	2021-06-02 06:51:09 +02:00
trace.h
xilinx_axidma.c
xlnx_csu_dma.c	hw/dma/xlnx_csu_dma: Always expect 'dma' link property to be set	2021-08-26 17:01:59 +01:00
xlnx_dpdma.c
xlnx-zdma.c	hw/dma/xlnx-zdma Always expect 'dma' link property to be set	2021-08-26 17:01:59 +01:00
xlnx-zynq-devcfg.c