Bin Meng 4c48aad122 target/riscv: Fix mret exception cause when no pmp rule is configured ... The priv spec v1.12 says: If no PMP entry matches an M-mode access, the access succeeds. If no PMP entry matches an S-mode or U-mode access, but at least one PMP entry is implemented, the access fails. Failed accesses generate an instruction, load, or store access-fault exception. At present the exception cause is set to 'illegal instruction' but should have been 'instruction access fault'. Fixes: d102f19a20 ("target/riscv/pmp: Raise exception if no PMP entry is configured") Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221205065303.204095-1-bmeng@tinylab.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2023-01-06 10:42:55 +10:00
..
insn_trans	target/riscv: Add itrigger support when icount is not enabled	2023-01-06 10:42:55 +10:00
arch_dump.c
bitmanip_helper.c
common-semi-target.h
cpu_bits.h	target/riscv: Add smstateen support	2023-01-06 10:42:55 +10:00
cpu_helper.c	target/riscv: support cache-related PMU events in virtual mode	2023-01-06 10:42:55 +10:00
cpu_user.h
cpu-param.h
cpu.c	target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state()	2023-01-06 10:42:55 +10:00
cpu.h	target/riscv: Add itrigger_enabled field to CPURISCVState	2023-01-06 10:42:55 +10:00
crypto_helper.c
csr.c	target/riscv: Typo fix in sstc() predicate	2023-01-06 10:42:55 +10:00
debug.c	target/riscv: Add itrigger_enabled field to CPURISCVState	2023-01-06 10:42:55 +10:00
debug.h	target/riscv: Add itrigger support when icount is enabled	2023-01-06 10:42:55 +10:00
fpu_helper.c
gdbstub.c
helper.h	target/riscv: Add itrigger support when icount is not enabled	2023-01-06 10:42:55 +10:00
insn16.decode
insn32.decode
instmap.h
internals.h
Kconfig
kvm_riscv.h
kvm-stub.c
kvm.c
m128_helper.c
machine.c	target/riscv: Add itrigger_enabled field to CPURISCVState	2023-01-06 10:42:55 +10:00
meson.build
monitor.c
op_helper.c	target/riscv: Fix mret exception cause when no pmp rule is configured	2023-01-06 10:42:55 +10:00
pmp.c	target/riscv: Fix PMP propagation for tlb	2023-01-06 10:42:55 +10:00
pmp.h	target/riscv: Fix PMP propagation for tlb	2023-01-06 10:42:55 +10:00
pmu.c
pmu.h
sbi_ecall_interface.h
time_helper.c
time_helper.h
trace-events
trace.h
translate.c	target/riscv: Add itrigger support when icount is not enabled	2023-01-06 10:42:55 +10:00
vector_helper.c	cleanup: Tweak and re-run return_directly.cocci	2022-12-14 16:19:35 +01:00
XVentanaCondOps.decode