Max Filippov 53593e90d1 target-xtensa: better control rsr/wsr/xsr access to SRs ... There are read-only (DEBUGCAUSE, PRID) and write-only (INTCLEAR) SRs, and INTERRUPT/INTSET SR allows rsr/wsr, but not xsr. Raise illeagal opcode exception on illegal access to these SRs. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>		2012-12-08 18:48:26 +00:00
..
core-dc232b	target-xtensa: add dc232b core	2011-10-16 10:40:02 +00:00
core-dc233c	target-xtensa: add dc233c core	2012-04-15 17:43:16 +00:00
core-fsf	target-xtensa: add fsf core	2011-10-16 10:40:16 +00:00
core-dc232b.c	target-xtensa: add license to core-dc232b.c	2012-04-15 17:43:28 +00:00
core-dc233c.c	target-xtensa: add dc233c core	2012-04-15 17:43:16 +00:00
core-fsf.c	target-xtensa: add license to core-fsf.c	2012-04-15 17:43:43 +00:00
cpu-qom.h	target-xtensa: QOM'ify CPU	2012-04-14 03:48:08 +04:00
cpu.c	target-xtensa: implement CACHEATTR SR	2012-12-08 18:48:26 +00:00
cpu.h	target-xtensa: restrict available SRs by enabled options	2012-12-08 18:48:26 +00:00
helper.c	target-xtensa: implement CACHEATTR SR	2012-12-08 18:48:26 +00:00
helper.h	target-xtensa: implement ATOMCTL SR	2012-12-08 18:48:26 +00:00
machine.c
Makefile.objs	target-xtensa: switch to AREG0-free mode	2012-06-10 20:09:22 +00:00
op_helper.c	target-xtensa: implement ATOMCTL SR	2012-12-08 18:48:26 +00:00
overlay_tool.h	target-xtensa: restrict available SRs by enabled options	2012-12-08 18:48:26 +00:00
translate.c	target-xtensa: better control rsr/wsr/xsr access to SRs	2012-12-08 18:48:26 +00:00
xtensa-semi.c	Rename target_phys_addr_t to hwaddr	2012-10-23 08:58:25 -05:00