Víctor Colombo 4e245a9e26 target/riscv: Remove condition guarding register zero for auipc and lui ... Commit 57c108b864 introduced gen_set_gpri(), which already contains a check for if the destination register is 'zero'. The check in auipc and lui are then redundant. This patch removes those checks. Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220610165517.47517-1-victor.colombo@eldorado.org.br> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2022-07-03 10:03:20 +10:00
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trans_privileged.c.inc
trans_rva.c.inc
trans_rvb.c.inc	target/riscv: rvk: add support for zbkx extension	2022-04-29 10:47:45 +10:00
trans_rvd.c.inc	target/riscv: add support for zdinx	2022-03-03 13:14:50 +10:00
trans_rvf.c.inc	target/riscv: add support for zfinx	2022-03-03 13:14:50 +10:00
trans_rvh.c.inc
trans_rvi.c.inc	target/riscv: Remove condition guarding register zero for auipc and lui	2022-07-03 10:03:20 +10:00
trans_rvk.c.inc	target/riscv: rvk: add support for zksed/zksh extension	2022-04-29 10:47:45 +10:00
trans_rvm.c.inc	target/riscv: add support for zmmul extension v0.1	2022-06-10 09:31:42 +10:00
trans_rvv.c.inc	target/riscv: trans_rvv: Avoid assert for RV32 and e64	2022-06-10 09:42:12 +10:00
trans_rvzfh.c.inc	target/riscv: add support for zhinx/zhinxmin	2022-03-03 13:14:50 +10:00
trans_svinval.c.inc
trans_xventanacondops.c.inc