qemu-e2k/target
Vladimir Isaev 5fc0fc8788 target/riscv: fix ctzw behavior
According to spec, ctzw should work with 32-bit register, not 64.

For example, previous implementation returns 33 for (1<<33) input
when the new one returns 32.

Signed-off-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230204082312.43557-1-vladimir.isaev@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-02-07 08:19:23 +10:00
..
alpha
arm target/arm: Use tcg_gen_atomic_cmpxchg_i128 for CASP 2023-02-04 06:19:42 -10:00
avr
cris
hexagon Hexagon (target/hexagon) implement mutability mask for GPRs 2023-01-05 09:19:02 -08:00
hppa target/hppa: Fix fid instruction emulation 2022-12-19 23:14:06 +01:00
i386 target/i386: Inline cmpxchg16b 2023-02-04 06:19:43 -10:00
loongarch target/loongarch: Disassemble pcadd* addresses 2023-01-23 15:36:36 -10:00
m68k m68k: fix 'bkpt' instruction in softmmu mode 2023-02-01 10:18:21 +01:00
microblaze bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx 2023-01-18 11:14:34 +01:00
mips bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx 2023-01-18 11:14:34 +01:00
nios2
openrisc target/openrisc: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
ppc target/ppc: Use tcg_gen_atomic_cmpxchg_i128 for STQCX 2023-02-04 06:19:42 -10:00
riscv target/riscv: fix ctzw behavior 2023-02-07 08:19:23 +10:00
rx target/rx: Convert to 3-phase reset 2022-12-16 15:58:16 +00:00
s390x target/s390x: Implement CC_OP_NZ in gen_op_calc_cc 2023-02-04 06:19:43 -10:00
sh4 target/sh4: Mask restore of env->flags from tb->flags 2022-12-18 09:36:07 -08:00
sparc bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx 2023-01-18 11:14:34 +01:00
tricore bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx 2023-01-18 11:14:34 +01:00
xtensa target/xtensa: Convert to 3-phase reset 2022-12-16 15:58:16 +00:00
Kconfig
meson.build