Kito Cheng 620455350a target/riscv: Fix wrong expanding for c.fswsp ... base register is no rs1 not rs2 for fsw. Signed-off-by: Kito Cheng <kito.cheng@gmail.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2019-03-26 03:17:30 -07:00
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alpha	avoid TABs in files that only contain a few	2019-01-11 15:46:56 +01:00
arm	Pull request	2019-03-25 17:01:10 +00:00
cris	avoid TABs in files that only contain a few	2019-01-11 15:46:56 +01:00
hppa	trace-events: Shorten file names in comments	2019-03-22 16:18:07 +00:00
i386	trace-events: Shorten file names in comments	2019-03-22 16:18:07 +00:00
lm32
m68k	target/m68k: Fix LGPL information in the file headers	2019-01-30 14:20:13 +01:00
microblaze	target/microblaze: Add props enabling exceptions on failed bus accesses	2019-01-22 03:17:34 -08:00
mips	trace-events: Shorten file names in comments	2019-03-22 16:18:07 +00:00
moxie	target/moxie: Fix LGPL information in the file headers	2019-02-06 15:46:11 +01:00
nios2
openrisc	target/openrisc: Fix LGPL version number	2019-01-30 11:01:36 +01:00
ppc	trace-events: Shorten file names in comments	2019-03-22 16:18:07 +00:00
riscv	target/riscv: Fix wrong expanding for c.fswsp	2019-03-26 03:17:30 -07:00
s390x	trace-events: Shorten file names in comments	2019-03-22 16:18:07 +00:00
sh4
sparc	trace-events: Shorten file names in comments	2019-03-22 16:18:07 +00:00
tilegx	avoid TABs in files that only contain a few	2019-01-11 15:46:56 +01:00
tricore	tricore: fixed RCR_CADDN instruction	2019-03-08 10:00:59 +01:00
unicore32
xtensa	target/xtensa: implement PREFCTL SR	2019-02-28 04:43:22 -08:00