..
insn_trans
target/riscv: Replace Zvbb checking by Zvkb
2023-11-07 11:06:02 +10:00
kvm
target/riscv/kvm: do not use non-portable strerrorname_np()
2023-12-23 19:29:56 +03:00
tcg
target/riscv: don't verify ISA compatibility for zicntr and zihpm
2023-11-22 13:56:13 +10:00
arch_dump.c
target/riscv: Fix format for comments
2023-05-05 10:49:50 +10:00
bitmanip_helper.c
common-semi-target.h
cpu_bits.h
target/riscv: Add M-mode virtual interrupt and IRQ filtering support.
2023-11-07 11:02:17 +10:00
cpu_cfg.h
target/riscv: Add "pmu-mask" property to replace "pmu-num"
2023-11-07 11:06:02 +10:00
cpu_helper.c
target/riscv/cpu_helper.c: Fix mxr bit behavior
2023-11-22 14:03:37 +10:00
cpu_user.h
cpu_vendorid.h
target/riscv: add Ventana's Veyron V1 CPU
2023-05-05 10:49:50 +10:00
cpu-param.h
target/riscv: Remove NB_MMU_MODES define
2023-03-13 06:44:37 -07:00
cpu-qom.h
target: Move ArchCPUClass definition to 'cpu.h'
2023-11-07 13:08:48 +01:00
cpu.c
hw/cpu: Call object_class_is_abstract() once in cpu_class_by_name()
2023-11-07 13:08:48 +01:00
cpu.h
target/riscv/cpu.h: spelling fix: separatly
2023-11-15 12:06:05 +03:00
crypto_helper.c
target/riscv: Use accelerated helper for AES64KS1I
2023-09-11 11:45:55 +10:00
csr.c
target/riscv: Don't assume PMU counters are continuous
2023-11-07 11:06:02 +10:00
debug.c
target/riscv: Allocate itrigger timers only once
2023-09-11 11:45:55 +10:00
debug.h
target/riscv: Allocate itrigger timers only once
2023-09-11 11:45:55 +10:00
fpu_helper.c
riscv: Add support for the Zfa extension
2023-07-10 22:29:20 +10:00
gdbstub.c
target/riscv: rename ext_icsr to ext_zicsr
2023-11-07 11:02:17 +10:00
helper.h
target/riscv: Add Zvksed ISA extension support
2023-09-11 11:45:55 +10:00
insn16.decode
target/riscv: add support for Zcmt extension
2023-05-05 10:49:50 +10:00
insn32.decode
target/riscv: Add Zvksed ISA extension support
2023-09-11 11:45:55 +10:00
instmap.h
internals.h
target/riscv: Use env_archcpu() in [check_]nanbox()
2023-11-07 12:13:27 +01:00
Kconfig
m128_helper.c
target/helpers: Remove unnecessary 'qemu/main-loop.h' header
2023-08-31 19:47:43 +02:00
machine.c
target/riscv: Constify VMState in machine.c
2023-12-29 11:17:30 +11:00
meson.build
target/riscv: move KVM only files to kvm subdir
2023-10-12 12:20:24 +10:00
monitor.c
riscv: spelling fixes
2023-09-08 13:08:52 +03:00
op_helper.c
target/helpers: Remove unnecessary 'qemu/main-loop.h' header
2023-08-31 19:47:43 +02:00
pmp.c
target/riscv: pmp: Ignore writes when RW=01
2023-11-07 11:06:02 +10:00
pmp.h
target/riscv: pmp: Clear pmp/smepmp bits on reset
2023-11-07 11:06:02 +10:00
pmu.c
target/riscv: Add "pmu-mask" property to replace "pmu-num"
2023-11-07 11:06:02 +10:00
pmu.h
target/riscv: Use existing PMU counter mask in FDT generation
2023-11-07 11:06:02 +10:00
riscv-qmp-cmds.c
target/riscv/riscv-qmp-cmds.c: check CPU accel in query-cpu-model-expansion
2023-11-07 11:06:02 +10:00
sbi_ecall_interface.h
target/riscv: Fix format for comments
2023-05-05 10:49:50 +10:00
time_helper.c
target/riscv: Simplify type conversion for CPURISCVState
2023-05-05 10:49:49 +10:00
time_helper.h
target/riscv: Simplify type conversion for CPURISCVState
2023-05-05 10:49:49 +10:00
trace-events
trace.h
translate.c
accel/tcg: Replace CPUState.env_ptr with cpu_env()
2023-10-04 11:03:54 -07:00
vcrypto_helper.c
target/riscv: Add Zvksed ISA extension support
2023-09-11 11:45:55 +10:00
vector_helper.c
target/riscv: Fix vfwmaccbf16.vf
2023-10-12 12:50:13 +10:00
vector_internals.c
target/riscv: Refactor some of the generic vector functionality
2023-09-11 11:45:54 +10:00
vector_internals.h
target/riscv: Refactor some of the generic vector functionality
2023-09-11 11:45:55 +10:00
xthead.decode
RISC-V: Adding XTheadFmv ISA extension
2023-02-07 08:19:23 +10:00
XVentanaCondOps.decode
zce_helper.c
target/riscv: add support for Zcmt extension
2023-05-05 10:49:50 +10:00
85b57d3d54