qemu-e2k/disas
Christoph Müllner a47842d166 riscv: Add support for the Zfa extension
This patch introduces the RISC-V Zfa extension, which introduces
additional floating-point instructions:
* fli (load-immediate) with pre-defined immediates
* fminm/fmaxm (like fmin/fmax but with different NaN behaviour)
* fround/froundmx (round to integer)
* fcvtmod.w.d (Modular Convert-to-Integer)
* fmv* to access high bits of float register bigger than XLEN
* Quiet comparison instructions (fleq/fltq)

Zfa defines its instructions in combination with the following extensions:
* single-precision floating-point (F)
* double-precision floating-point (D)
* quad-precision floating-point (Q)
* half-precision floating-point (Zfh)

Since QEMU does not support the RISC-V quad-precision floating-point
ISA extension (Q), this patch does not include the instructions that
depend on this extension. All other instructions are included in this
patch.

The Zfa specification can be found here:
  https://github.com/riscv/riscv-isa-manual/blob/master/src/zfa.tex
The Zfa specifciation is frozen and is in public review since May 3, 2023:
  https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/SED4ntBkabg

The patch also includes a TCG test for the fcvtmod.w.d instruction.
The test cases test for correct results and flag behaviour.
Note, that the Zfa specification requires fcvtmod's flag behaviour
to be identical to a fcvt with the same operands (which is also
tested).

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230710071243.282464-1-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-07-10 22:29:20 +10:00
..
alpha.c
capstone.c disas: use result of ->read_memory_func 2022-10-06 11:53:40 +01:00
cris.c
disas-internal.h disas: Move softmmu specific code to separate file 2023-05-11 09:49:55 +01:00
disas-mon.c disas: Move softmmu specific code to separate file 2023-05-11 09:49:55 +01:00
disas.c disas: Move disas.c into the target-independent source set 2023-05-11 09:51:07 +01:00
hexagon.c
hppa.c
m68k.c
meson.build disas/riscv: Add support for XThead* instructions 2023-07-10 22:29:14 +10:00
microblaze.c
mips.c disas/mips: Fix branch displacement for BEQZC and BNEZC 2022-10-31 11:32:07 +01:00
nanomips.c disas/nanomips: Tidy read for 48-bit opcodes 2022-11-08 01:04:25 +01:00
nios2.c disas/nios2: Simplify endianess conversion 2021-10-22 18:07:30 +02:00
riscv-xthead.c disas/riscv: Add support for XThead* instructions 2023-07-10 22:29:14 +10:00
riscv-xthead.h disas/riscv: Add support for XThead* instructions 2023-07-10 22:29:14 +10:00
riscv-xventana.c disas/riscv: Add support for XVentanaCondOps 2023-07-10 22:29:14 +10:00
riscv-xventana.h disas/riscv: Add support for XVentanaCondOps 2023-07-10 22:29:14 +10:00
riscv.c riscv: Add support for the Zfa extension 2023-07-10 22:29:20 +10:00
riscv.h riscv: Add support for the Zfa extension 2023-07-10 22:29:20 +10:00
sh4.c
sparc.c
xtensa.c