456 lines
14 KiB
C
456 lines
14 KiB
C
/*
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* QEMU NE2000 emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h"
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/* debug NE2000 card */
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//#define DEBUG_NE2000
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#define MAX_ETH_FRAME_SIZE 1514
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#define E8390_CMD 0x00 /* The command register (for all pages) */
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/* Page 0 register offsets. */
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#define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
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#define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
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#define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
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#define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
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#define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
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#define EN0_TSR 0x04 /* Transmit status reg RD */
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#define EN0_TPSR 0x04 /* Transmit starting page WR */
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#define EN0_NCR 0x05 /* Number of collision reg RD */
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#define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
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#define EN0_FIFO 0x06 /* FIFO RD */
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#define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
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#define EN0_ISR 0x07 /* Interrupt status reg RD WR */
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#define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
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#define EN0_RSARLO 0x08 /* Remote start address reg 0 */
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#define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
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#define EN0_RSARHI 0x09 /* Remote start address reg 1 */
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#define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
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#define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
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#define EN0_RSR 0x0c /* rx status reg RD */
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#define EN0_RXCR 0x0c /* RX configuration reg WR */
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#define EN0_TXCR 0x0d /* TX configuration reg WR */
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#define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
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#define EN0_DCFG 0x0e /* Data configuration reg WR */
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#define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
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#define EN0_IMR 0x0f /* Interrupt mask reg WR */
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#define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
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#define EN1_PHYS 0x11
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#define EN1_CURPAG 0x17
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#define EN1_MULT 0x18
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/* Register accessed at EN_CMD, the 8390 base addr. */
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#define E8390_STOP 0x01 /* Stop and reset the chip */
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#define E8390_START 0x02 /* Start the chip, clear reset */
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#define E8390_TRANS 0x04 /* Transmit a frame */
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#define E8390_RREAD 0x08 /* Remote read */
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#define E8390_RWRITE 0x10 /* Remote write */
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#define E8390_NODMA 0x20 /* Remote DMA */
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#define E8390_PAGE0 0x00 /* Select page chip registers */
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#define E8390_PAGE1 0x40 /* using the two high-order bits */
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#define E8390_PAGE2 0x80 /* Page 3 is invalid. */
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/* Bits in EN0_ISR - Interrupt status register */
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#define ENISR_RX 0x01 /* Receiver, no error */
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#define ENISR_TX 0x02 /* Transmitter, no error */
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#define ENISR_RX_ERR 0x04 /* Receiver, with error */
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#define ENISR_TX_ERR 0x08 /* Transmitter, with error */
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#define ENISR_OVER 0x10 /* Receiver overwrote the ring */
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#define ENISR_COUNTERS 0x20 /* Counters need emptying */
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#define ENISR_RDC 0x40 /* remote dma complete */
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#define ENISR_RESET 0x80 /* Reset completed */
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#define ENISR_ALL 0x3f /* Interrupts we will enable */
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/* Bits in received packet status byte and EN0_RSR*/
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#define ENRSR_RXOK 0x01 /* Received a good packet */
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#define ENRSR_CRC 0x02 /* CRC error */
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#define ENRSR_FAE 0x04 /* frame alignment error */
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#define ENRSR_FO 0x08 /* FIFO overrun */
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#define ENRSR_MPA 0x10 /* missed pkt */
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#define ENRSR_PHY 0x20 /* physical/multicast address */
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#define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
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#define ENRSR_DEF 0x80 /* deferring */
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/* Transmitted packet status, EN0_TSR. */
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#define ENTSR_PTX 0x01 /* Packet transmitted without error */
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#define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
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#define ENTSR_COL 0x04 /* The transmit collided at least once. */
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#define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
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#define ENTSR_CRS 0x10 /* The carrier sense was lost. */
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#define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
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#define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
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#define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
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#define NE2000_MEM_SIZE 32768
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typedef struct NE2000State {
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uint8_t cmd;
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uint32_t start;
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uint32_t stop;
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uint8_t boundary;
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uint8_t tsr;
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uint8_t tpsr;
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uint16_t tcnt;
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uint16_t rcnt;
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uint32_t rsar;
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uint8_t isr;
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uint8_t dcfg;
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uint8_t imr;
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uint8_t phys[6]; /* mac address */
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uint8_t curpag;
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uint8_t mult[8]; /* multicast mask array */
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int irq;
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NetDriverState *nd;
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uint8_t mem[NE2000_MEM_SIZE];
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} NE2000State;
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static void ne2000_reset(NE2000State *s)
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{
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int i;
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s->isr = ENISR_RESET;
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memcpy(s->mem, s->nd->macaddr, 6);
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s->mem[14] = 0x57;
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s->mem[15] = 0x57;
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/* duplicate prom data */
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for(i = 15;i >= 0; i--) {
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s->mem[2 * i] = s->mem[i];
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s->mem[2 * i + 1] = s->mem[i];
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}
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}
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static void ne2000_update_irq(NE2000State *s)
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{
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int isr;
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isr = s->isr & s->imr;
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if (isr)
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pic_set_irq(s->irq, 1);
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else
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pic_set_irq(s->irq, 0);
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}
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/* return the max buffer size if the NE2000 can receive more data */
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static int ne2000_can_receive(void *opaque)
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{
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NE2000State *s = opaque;
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int avail, index, boundary;
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if (s->cmd & E8390_STOP)
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return 0;
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index = s->curpag << 8;
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boundary = s->boundary << 8;
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if (index < boundary)
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avail = boundary - index;
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else
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avail = (s->stop - s->start) - (index - boundary);
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if (avail < (MAX_ETH_FRAME_SIZE + 4))
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return 0;
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return MAX_ETH_FRAME_SIZE;
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}
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#define MIN_BUF_SIZE 60
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static void ne2000_receive(void *opaque, const uint8_t *buf, int size)
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{
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NE2000State *s = opaque;
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uint8_t *p;
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int total_len, next, avail, len, index;
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uint8_t buf1[60];
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#if defined(DEBUG_NE2000)
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printf("NE2000: received len=%d\n", size);
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#endif
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/* if too small buffer, then expand it */
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if (size < MIN_BUF_SIZE) {
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memcpy(buf1, buf, size);
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memset(buf1 + size, 0, MIN_BUF_SIZE - size);
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buf = buf1;
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size = MIN_BUF_SIZE;
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}
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index = s->curpag << 8;
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/* 4 bytes for header */
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total_len = size + 4;
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/* address for next packet (4 bytes for CRC) */
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next = index + ((total_len + 4 + 255) & ~0xff);
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if (next >= s->stop)
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next -= (s->stop - s->start);
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/* prepare packet header */
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p = s->mem + index;
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p[0] = ENRSR_RXOK; /* receive status */
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p[1] = next >> 8;
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p[2] = total_len;
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p[3] = total_len >> 8;
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index += 4;
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/* write packet data */
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while (size > 0) {
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avail = s->stop - index;
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len = size;
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if (len > avail)
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len = avail;
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memcpy(s->mem + index, buf, len);
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buf += len;
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index += len;
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if (index == s->stop)
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index = s->start;
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size -= len;
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}
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s->curpag = next >> 8;
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/* now we can signal we have receive something */
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s->isr |= ENISR_RX;
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ne2000_update_irq(s);
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}
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static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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{
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NE2000State *s = opaque;
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int offset, page;
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addr &= 0xf;
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#ifdef DEBUG_NE2000
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printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
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#endif
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if (addr == E8390_CMD) {
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/* control register */
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s->cmd = val;
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if (val & E8390_START) {
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/* test specific case: zero length transfert */
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if ((val & (E8390_RREAD | E8390_RWRITE)) &&
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s->rcnt == 0) {
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s->isr |= ENISR_RDC;
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ne2000_update_irq(s);
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}
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if (val & E8390_TRANS) {
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net_send_packet(s->nd, s->mem + (s->tpsr << 8), s->tcnt);
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/* signal end of transfert */
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s->tsr = ENTSR_PTX;
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s->isr |= ENISR_TX;
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ne2000_update_irq(s);
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}
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}
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} else {
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page = s->cmd >> 6;
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offset = addr | (page << 4);
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switch(offset) {
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case EN0_STARTPG:
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s->start = val << 8;
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break;
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case EN0_STOPPG:
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s->stop = val << 8;
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break;
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case EN0_BOUNDARY:
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s->boundary = val;
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break;
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case EN0_IMR:
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s->imr = val;
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ne2000_update_irq(s);
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break;
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case EN0_TPSR:
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s->tpsr = val;
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break;
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case EN0_TCNTLO:
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s->tcnt = (s->tcnt & 0xff00) | val;
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break;
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case EN0_TCNTHI:
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s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
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break;
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case EN0_RSARLO:
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s->rsar = (s->rsar & 0xff00) | val;
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break;
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case EN0_RSARHI:
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s->rsar = (s->rsar & 0x00ff) | (val << 8);
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break;
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case EN0_RCNTLO:
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s->rcnt = (s->rcnt & 0xff00) | val;
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break;
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case EN0_RCNTHI:
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s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
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break;
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case EN0_DCFG:
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s->dcfg = val;
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break;
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case EN0_ISR:
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s->isr &= ~val;
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ne2000_update_irq(s);
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break;
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case EN1_PHYS ... EN1_PHYS + 5:
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s->phys[offset - EN1_PHYS] = val;
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break;
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case EN1_CURPAG:
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s->curpag = val;
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break;
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case EN1_MULT ... EN1_MULT + 7:
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s->mult[offset - EN1_MULT] = val;
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break;
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}
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}
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}
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static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
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{
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NE2000State *s = opaque;
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int offset, page, ret;
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addr &= 0xf;
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if (addr == E8390_CMD) {
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ret = s->cmd;
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} else {
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page = s->cmd >> 6;
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offset = addr | (page << 4);
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switch(offset) {
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case EN0_TSR:
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ret = s->tsr;
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break;
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case EN0_BOUNDARY:
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ret = s->boundary;
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break;
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case EN0_ISR:
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ret = s->isr;
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break;
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case EN1_PHYS ... EN1_PHYS + 5:
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ret = s->phys[offset - EN1_PHYS];
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break;
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case EN1_CURPAG:
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ret = s->curpag;
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break;
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case EN1_MULT ... EN1_MULT + 7:
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ret = s->mult[offset - EN1_MULT];
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break;
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default:
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ret = 0x00;
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break;
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}
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}
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#ifdef DEBUG_NE2000
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printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
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#endif
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return ret;
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}
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static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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{
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NE2000State *s = opaque;
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uint8_t *p;
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#ifdef DEBUG_NE2000
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printf("NE2000: asic write val=0x%04x\n", val);
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#endif
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p = s->mem + s->rsar;
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if (s->dcfg & 0x01) {
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/* 16 bit access */
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p[0] = val;
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p[1] = val >> 8;
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s->rsar += 2;
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s->rcnt -= 2;
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} else {
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/* 8 bit access */
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p[0] = val;
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s->rsar++;
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s->rcnt--;
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}
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/* wrap */
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if (s->rsar == s->stop)
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s->rsar = s->start;
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if (s->rcnt == 0) {
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/* signal end of transfert */
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s->isr |= ENISR_RDC;
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ne2000_update_irq(s);
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}
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}
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static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
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{
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NE2000State *s = opaque;
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uint8_t *p;
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int ret;
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p = s->mem + s->rsar;
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if (s->dcfg & 0x01) {
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/* 16 bit access */
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ret = p[0] | (p[1] << 8);
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s->rsar += 2;
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s->rcnt -= 2;
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} else {
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/* 8 bit access */
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ret = p[0];
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s->rsar++;
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s->rcnt--;
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}
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/* wrap */
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if (s->rsar == s->stop)
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s->rsar = s->start;
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if (s->rcnt == 0) {
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/* signal end of transfert */
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s->isr |= ENISR_RDC;
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ne2000_update_irq(s);
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}
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#ifdef DEBUG_NE2000
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printf("NE2000: asic read val=0x%04x\n", ret);
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#endif
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return ret;
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}
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static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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{
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/* nothing to do (end of reset pulse) */
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}
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static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
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{
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NE2000State *s = opaque;
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ne2000_reset(s);
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return 0;
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}
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void ne2000_init(int base, int irq, NetDriverState *nd)
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{
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NE2000State *s;
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s = qemu_mallocz(sizeof(NE2000State));
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if (!s)
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return;
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register_ioport_write(base, 16, 1, ne2000_ioport_write, s);
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register_ioport_read(base, 16, 1, ne2000_ioport_read, s);
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register_ioport_write(base + 0x10, 1, 1, ne2000_asic_ioport_write, s);
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register_ioport_read(base + 0x10, 1, 1, ne2000_asic_ioport_read, s);
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register_ioport_write(base + 0x10, 2, 2, ne2000_asic_ioport_write, s);
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register_ioport_read(base + 0x10, 2, 2, ne2000_asic_ioport_read, s);
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register_ioport_write(base + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
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register_ioport_read(base + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
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s->irq = irq;
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s->nd = nd;
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ne2000_reset(s);
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qemu_add_fd_read_handler(nd->fd, ne2000_can_receive, ne2000_receive, s);
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}
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