qemu-e2k/target
Marc Zyngier 6a4ef4e5d1 target/arm: Honor HCR_EL2.TID3 trapping requirements
HCR_EL2.TID3 mandates that access from EL1 to a long list of id
registers traps to EL2, and QEMU has so far ignored this requirement.

This breaks (among other things) KVM guests that have PtrAuth enabled,
while the hypervisor doesn't want to expose the feature to its guest.
To achieve this, KVM traps the ID registers (ID_AA64ISAR1_EL1 in this
case), and masks out the unsupported feature.

QEMU not honoring the trap request means that the guest observes
that the feature is present in the HW, starts using it, and dies
a horrible death when KVM injects an UNDEF, because the feature
*really* isn't supported.

Do the right thing by trapping to EL2 if HCR_EL2.TID3 is set.

Note that this change does not include trapping of the MVFR
registers from AArch32 (they are accessed via the VMRS
instruction and need to be handled in a different way).

Reported-by: Will Deacon <will@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Tested-by: Will Deacon <will@kernel.org>
Message-id: 20191123115618.29230-1-maz@kernel.org
[PMM: added missing accessfn line for ID_AA4PFR2_EL1_RESERVED;
 changed names of access functions to include _tid3]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-11-26 13:55:37 +00:00
..
alpha target/alpha: fetch code with translator_ld 2019-10-28 15:12:38 +00:00
arm target/arm: Honor HCR_EL2.TID3 trapping requirements 2019-11-26 13:55:37 +00:00
cris cputlb: ensure _cmmu helper functions follow the naming standard 2019-10-28 15:12:38 +00:00
hppa target/hppa: fetch code with translator_ld 2019-10-28 15:12:38 +00:00
i386 i386: Add -noTSX aliases for hle=off, rtm=off CPU models 2019-11-21 16:35:05 +01:00
lm32 Monitor patches for 2019-08-21 2019-08-22 10:31:21 +01:00
m68k target/m68k: fetch code with translator_ld 2019-10-28 15:12:38 +00:00
microblaze target/microblaze: Plug temp leak around eval_cond_jmp() 2019-11-12 16:35:26 +01:00
mips target/mips: Refactor handling of vector compare 'less than' (signed) instructions 2019-10-25 18:37:01 +02:00
moxie hw/core: Move cpu.c, cpu.h from qom/ to hw/core/ 2019-08-21 13:24:01 +02:00
nios2 Monitor patches for 2019-08-21 2019-08-22 10:31:21 +01:00
openrisc target/openrisc: fetch code with translator_ld 2019-10-28 15:12:38 +00:00
ppc spapr/kvm: Set default cpu model for all machine classes 2019-11-18 11:50:39 +01:00
riscv target/riscv: Remove atomic accesses to MIP CSR 2019-11-14 09:53:28 -08:00
s390x s390x/kvm: Set default cpu model for all machine classes 2019-10-21 18:03:08 +02:00
sh4 target/sh4: fetch code with translator_ld 2019-10-28 15:12:38 +00:00
sparc target/sparc: Define an enumeration for accessing env->regwptr 2019-11-06 13:35:25 +01:00
tilegx tcg: TCGMemOp is now accelerator independent MemOp 2019-09-03 08:30:38 -07:00
tricore tcg: TCGMemOp is now accelerator independent MemOp 2019-09-03 08:30:38 -07:00
unicore32 Monitor patches for 2019-08-21 2019-08-22 10:31:21 +01:00
xtensa target/xtensa: fetch code with translator_ld 2019-10-28 15:12:38 +00:00