Corey Wharton d784733bf1 target/riscv: Add a sifive-e34 cpu type ... The sifive-e34 cpu type is the same as the sifive-e31 with the single precision floating-point extension enabled. Signed-off-by: Corey Wharton <coreyw7@fb.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20200313193429.8035-3-coreyw7@fb.com Message-Id: <20200313193429.8035-3-coreyw7@fb.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2020-04-29 13:16:37 -07:00
..
insn_trans	target/riscv: Remove the hret instruction	2020-02-27 13:45:45 -08:00
cpu_bits.h	target/riscv: Add the MSTATUS_MPV_ISSET helper macro	2020-02-27 13:46:33 -08:00
cpu_helper.c	riscv: Fix Stage2 SV32 page table walk	2020-04-29 13:16:37 -07:00
cpu_user.h
cpu-param.h
cpu.c	target/riscv: Add a sifive-e34 cpu type	2020-04-29 13:16:37 -07:00
cpu.h	target/riscv: Add a sifive-e34 cpu type	2020-04-29 13:16:37 -07:00
csr.c	target/riscv: Emulate TIME CSRs for privileged mode	2020-02-27 13:46:36 -08:00
fpu_helper.c
gdbstub.c	gdbstub: extend GByteArray to read register helpers	2020-03-17 17:38:38 +00:00
helper.h
insn16-32.decode
insn16-64.decode
insn16.decode
insn32-64.decode
insn32.decode	target/riscv: Remove the hret instruction	2020-02-27 13:45:45 -08:00
instmap.h
Makefile.objs
monitor.c
op_helper.c	target/riscv: Correctly implement TSR trap	2020-03-16 17:03:13 -07:00
pmp.c
pmp.h
trace-events
translate.c	target/riscv: Add the MSTATUS_MPV_ISSET helper macro	2020-02-27 13:46:33 -08:00