Taylor Simpson 6c677c60ae Hexagon (target/hexagon) decide if pred has been written at TCG gen time ... Multiple writes to the same preg are and'ed together. Rather than generating a runtime check, we can determine at TCG generation time if the predicate has previously been written in the packet. Test added to tests/tcg/hexagon/misc.c Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1617930474-31979-7-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>		2021-05-01 08:31:43 -07:00
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alpha
arm	target/arm: Enforce alignment for sve LD1R	2021-04-30 11:16:51 +01:00
avr
cris
hexagon	Hexagon (target/hexagon) decide if pred has been written at TCG gen time	2021-05-01 08:31:43 -07:00
hppa
i386	i386: Add missing cpu feature bits in EPYC-Rome model	2021-04-09 16:02:18 -04:00
lm32
m68k
microblaze
mips	target/mips/rel6_translate: Change license to GNU LGPL v2.1 (or later)	2021-04-20 12:52:04 +01:00
moxie
nios2
openrisc
ppc
riscv
rx
s390x	target/s390x: fix s390_probe_access to check PAGE_WRITE_ORG for writeability	2021-04-23 14:10:56 +01:00
sh4
sparc
tricore
unicore32
xtensa
meson.build