qemu-e2k/target
Philippe Mathieu-Daudé 744c72a837 cpu: Rename CPUClass vmsd -> legacy_vmsd
Quoting Peter Maydell [*]:

  There are two ways to handle migration for
  a CPU object:

  (1) like any other device, so it has a dc->vmsd that covers
  migration for the whole object. As usual for objects that are a
  subclass of a parent that has state, the first entry in the
  VMStateDescription field list is VMSTATE_CPU(), which migrates
  the cpu_common fields, followed by whatever the CPU's own migration
  fields are.

  (2) a backwards-compatible mechanism for CPUs that were
  originally migrated using manual "write fields to the migration
  stream structures". The on-the-wire migration format
  for those is based on the 'env' pointer (which isn't a QOM object),
  and the cpu_common part of the migration data is elsewhere.

  cpu_exec_realizefn() handles both possibilities:

  * for type 1, dc->vmsd is set and cc->vmsd is not,
    so cpu_exec_realizefn() does nothing, and the standard
    "register dc->vmsd for a device" code does everything needed

  * for type 2, dc->vmsd is NULL and so we register the
    vmstate_cpu_common directly to handle the cpu-common fields,
    and the cc->vmsd to handle the per-CPU stuff

  You can't change a CPU from one type to the other without breaking
  migration compatibility, which is why some guest architectures
  are stuck on the cc->vmsd form. New targets should use dc->vmsd.

To avoid new targets to start using type (2), rename cc->vmsd as
cc->legacy_vmsd. The correct field to implement is dc->vmsd (the
DeviceClass one).

See also commit b170fce3dd ("cpu: Register VMStateDescription
through CPUState") for historic background.

[*] https://www.mail-archive.com/qemu-devel@nongnu.org/msg800849.html

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Cc: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20210517105140.1062037-13-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-26 15:33:59 -07:00
..
alpha target/alpha: fix icount handling for timer instructions 2021-04-05 07:32:56 -07:00
arm cpu: Rename CPUClass vmsd -> legacy_vmsd 2021-05-26 15:33:59 -07:00
avr cpu: Rename CPUClass vmsd -> legacy_vmsd 2021-05-26 15:33:59 -07:00
cris target/cris: Plug leakage of TCG temporaries 2021-02-22 09:04:58 +01:00
hexagon Trivial patches pull request 20210503 2021-05-05 13:52:00 +01:00
hppa exec: Use cpu_untagged_addr in g2h; split out g2h_untagged 2021-02-16 11:04:53 +00:00
i386 cpu: Rename CPUClass vmsd -> legacy_vmsd 2021-05-26 15:33:59 -07:00
m68k Prepare MacOS ROM support: 2021-03-12 18:56:56 +00:00
microblaze cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass 2021-02-05 10:24:15 -10:00
mips cpu: Rename CPUClass vmsd -> legacy_vmsd 2021-05-26 15:33:59 -07:00
nios2 semihosting: Move include/hw/semihosting/ -> include/semihosting/ 2021-03-10 15:34:12 +00:00
openrisc Do not include sysemu/sysemu.h if it's not really necessary 2021-05-02 17:24:50 +02:00
ppc cpu: Rename CPUClass vmsd -> legacy_vmsd 2021-05-26 15:33:59 -07:00
riscv cpu: Rename CPUClass vmsd -> legacy_vmsd 2021-05-26 15:33:59 -07:00
rx Do not include sysemu/sysemu.h if it's not really necessary 2021-05-02 17:24:50 +02:00
s390x cpu: Rename CPUClass vmsd -> legacy_vmsd 2021-05-26 15:33:59 -07:00
sh4 cpu: Assert DeviceClass::vmsd is NULL on user emulation 2021-05-26 15:33:59 -07:00
sparc cpu: Rename CPUClass vmsd -> legacy_vmsd 2021-05-26 15:33:59 -07:00
tricore target/tricore: Fix OPC2_32_RRPW_EXTR for width=0 2021-03-14 14:49:01 +01:00
xtensa cpu: Assert DeviceClass::vmsd is NULL on user emulation 2021-05-26 15:33:59 -07:00
meson.build Drop the deprecated unicore32 target 2021-05-12 18:20:52 +02:00