Richard Henderson 401aa608d8 target/riscv: Use insn_start from DisasContextBase ... To keep the multiple update check, replace insn_start with insn_start_updated. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>		2024-04-09 07:45:09 -10:00
..
insn_trans	target/riscv: enable 'vstart_eq_zero' in the end of insns	2024-03-22 15:24:37 +10:00
kvm	target/riscv/kvm: fix timebase-frequency when using KVM acceleration	2024-03-22 15:41:01 +10:00
tcg	target/riscv: rvv: Remove the dependency of Zvfbfmin to Zfbfmin	2024-03-22 15:31:09 +10:00
arch_dump.c
bitmanip_helper.c
common-semi-target.h
cpu_bits.h	target/riscv: FCSR doesn't contain vxrm and vxsat	2024-02-09 20:43:14 +10:00
cpu_cfg.h	target/riscv: do not enable all named features by default	2024-03-22 15:10:45 +10:00
cpu_helper.c	target/riscv: Fix mode in riscv_tlb_fill	2024-03-22 15:32:33 +10:00
cpu_user.h
cpu_vendorid.h
cpu-param.h
cpu-qom.h	target/riscv: add rv32i, rv32e and rv64e CPUs	2024-02-09 20:49:41 +10:00
cpu.c	target/riscv: do not enable all named features by default	2024-03-22 15:10:45 +10:00
cpu.h	target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit	2024-03-08 20:48:03 +10:00
crypto_helper.c
csr.c	target/riscv: UPDATE xATP write CSR	2024-03-08 16:38:09 +10:00
debug.c	target/riscv: Implement optional CSR mcontext of debug Sdtrig extension	2024-02-09 20:40:32 +10:00
debug.h
fpu_helper.c
gdbstub.c	gdbstub: Add members to identify registers to GDBFeature	2024-02-28 09:10:11 +00:00
helper.h
insn16.decode
insn32.decode	target/riscv: Add support for Zacas extension	2024-01-10 18:47:47 +10:00
instmap.h
internals.h	target/riscv: Use env_archcpu() in [check_]nanbox()	2023-11-07 12:13:27 +01:00
Kconfig	kconfig: use "select" to enable semihosting	2024-02-09 17:52:30 +00:00
m128_helper.c
machine.c	target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit	2024-03-08 20:48:03 +10:00
meson.build
monitor.c
op_helper.c	target/riscv: Replace cpu_mmu_index with riscv_env_mmu_index	2024-02-03 16:46:10 +10:00
pmp.c	target/riscv: pmp: Ignore writes when RW=01 and MML=0	2024-01-10 18:47:47 +10:00
pmp.h	target/riscv/pmp: Use hwaddr instead of target_ulong for RV32	2024-01-10 18:47:46 +10:00
pmu.c	target/riscv: Add "pmu-mask" property to replace "pmu-num"	2023-11-07 11:06:02 +10:00
pmu.h	target/riscv: Add missing include guard in pmu.h	2024-03-08 16:39:32 +10:00
riscv-qmp-cmds.c	target: Improve error reporting for CpuModelInfo member @props	2024-03-12 14:03:00 +01:00
sbi_ecall_interface.h
time_helper.c
time_helper.h
trace-events
trace.h
translate.c	target/riscv: Use insn_start from DisasContextBase	2024-04-09 07:45:09 -10:00
vcrypto_helper.c	target/riscv/vector_helpers: do early exit when vstart >= vl	2024-03-22 15:20:02 +10:00
vector_helper.c	target/riscv/vector_helper.c: optimize loops in ldst helpers	2024-03-22 15:28:19 +10:00
vector_internals.c	target/riscv/vector_helpers: do early exit when vstart >= vl	2024-03-22 15:20:02 +10:00
vector_internals.h	target/riscv/vector_helpers: do early exit when vstart >= vl	2024-03-22 15:20:02 +10:00
xthead.decode
XVentanaCondOps.decode
zce_helper.c