eopXD 7b1bff41c1 target/riscv: rvv: Add tail agnostic for vector integer shift instructions ... Signed-off-by: eop Chen <eop.chen@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <165449614532.19704.7000832880482980398-8@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2022-06-10 09:31:42 +10:00
..
insn_trans	target/riscv: rvv: Add tail agnostic for vector integer shift instructions	2022-06-10 09:31:42 +10:00
arch_dump.c
bitmanip_helper.c
cpu_bits.h	target/riscv: rvk: add CSR support for Zkr	2022-04-29 10:47:45 +10:00
cpu_helper.c	target/riscv: rvv: Add tail agnostic for vv instructions	2022-06-10 09:31:42 +10:00
cpu_user.h
cpu-param.h	Normalize header guard symbol definition	2022-05-11 16:50:26 +02:00
cpu.c	target/riscv: Wake on VS-level external interrupts	2022-06-10 09:31:42 +10:00
cpu.h	target/riscv: rvv: Add tail agnostic for vv instructions	2022-06-10 09:31:42 +10:00
crypto_helper.c	target/riscv: rvk: add support for zksed/zksh extension	2022-04-29 10:47:45 +10:00
csr.c	target/riscv: Fix csr number based privilege checking	2022-05-24 10:38:50 +10:00
debug.c	target/riscv/debug.c: keep experimental rv128 support working	2022-06-10 09:31:42 +10:00
debug.h
fpu_helper.c
gdbstub.c
helper.h	target/riscv: rvk: add support for zksed/zksh extension	2022-04-29 10:47:45 +10:00
insn16.decode
insn32.decode	target/riscv: rvk: add support for zksed/zksh extension	2022-04-29 10:47:45 +10:00
instmap.h
internals.h	target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions	2022-06-10 09:31:42 +10:00
Kconfig
kvm_riscv.h
kvm-stub.c
kvm.c
m128_helper.c
machine.c
meson.build
monitor.c	target/riscv: Fix incorrect PTE merge in walk_pte	2022-04-29 10:47:46 +10:00
op_helper.c	target/riscv: rvk: add CSR support for Zkr	2022-04-29 10:47:45 +10:00
pmp.c
pmp.h	target/riscv: rvk: add CSR support for Zkr	2022-04-29 10:47:45 +10:00
sbi_ecall_interface.h	Clean up ill-advised or unusual header guards	2022-05-11 16:50:01 +02:00
trace-events
trace.h
translate.c	target/riscv: rvv: Add tail agnostic for vector load / store instructions	2022-06-10 09:31:42 +10:00
vector_helper.c	target/riscv: rvv: Add tail agnostic for vector integer shift instructions	2022-06-10 09:31:42 +10:00
XVentanaCondOps.decode