Maciej W. Rozycki 800675f117 target-mips: Correct the handling of register #72 on writes ... Fix an off-by-one error in `mips_cpu_gdb_write_register' for register matching how `mips_cpu_gdb_read_register' handles it. This register slot is a fake anyway, there's nothing in hardware that corresponds to it. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>		2014-12-16 12:45:19 +00:00
..
cpu-qom.h	target-mips: Use cpu_exec_interrupt qom hook	2014-09-25 18:54:22 +01:00
cpu.c	gdbstub: Allow target CPUs to specify watchpoint STOP_BEFORE_ACCESS flag	2014-10-06 14:25:43 +01:00
cpu.h	mips: Add macros for CP0.Config3 and CP0.Config4 bits	2014-11-07 14:15:28 +00:00
dsp_helper.c	target-mips/dsp_helper.c: Add ifdef guards around various functions	2014-10-14 13:29:14 +01:00
gdbstub.c	target-mips: Correct the handling of register #72 on writes	2014-12-16 12:45:19 +00:00
helper.c	target-mips: add MSA exceptions	2014-11-03 11:48:35 +00:00
helper.h	target-mips: add MSA MI10 format instructions	2014-11-03 11:48:35 +00:00
kvm_mips.h	target-mips: kvm: Add main KVM support for MIPS	2014-06-18 16:58:52 +02:00
kvm.c	target-mips: kvm: do not use get_clock()	2014-12-15 12:21:01 +01:00
lmi_helper.c	tcg: Invert the inclusion of helper.h	2014-05-28 09:33:54 -07:00
machine.c	target-mips: update cpu_save/cpu_load to support new registers	2014-11-03 11:48:34 +00:00
Makefile.objs	target-mips: add msa_helper.c	2014-11-03 11:48:35 +00:00
mips-defs.h	target-mips: add MSA defines and data structure	2014-11-03 11:48:35 +00:00
msa_helper.c	target-mips: add MSA 2RF format instructions	2014-11-03 11:48:35 +00:00
op_helper.c	target-mips: add MSA MI10 format instructions	2014-11-03 11:48:35 +00:00
TODO	target-mips: Change TODO file	2012-10-31 21:37:24 +01:00
translate_init.c	mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bits	2014-11-07 14:15:28 +00:00
translate.c	target-mips: fix multiple TCG registers covering same data	2014-11-07 14:15:28 +00:00