Jiaxun Yang 8063db0fc8 target/mips: Set CP0St_{KX, SX, UX} for Loongson-2F ... As per an unpublished document, in later reversion of chips CP0St_{KX, SX, UX} is not writeable and hardcoded to 1. Without those bits set, kernel is unable to access XKPHYS address segment. So just set them up on CPU reset. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221031132531.18122-2-jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>		2022-11-08 01:04:25 +01:00
..
sysemu
tcg	target/mips: Convert to tcg_ops restore_state_to_opc	2022-10-26 11:11:28 +10:00
cpu-defs.c.inc	target/mips: introduce Cavium Octeon CPU model	2022-07-12 22:30:26 +02:00
cpu-param.h	Normalize header guard symbol definition	2022-05-11 16:50:26 +02:00
cpu-qom.h	target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macro	2022-03-06 22:23:09 +01:00
cpu.c	target/mips: Set CP0St_{KX, SX, UX} for Loongson-2F	2022-11-08 01:04:25 +01:00
cpu.h	target/mips: Use an exception for semihosting	2022-06-28 10:13:42 +05:30
fpu_helper.h
fpu.c
gdbstub.c
helper.h
internal.h	MIPS patches queue	2022-03-09 09:13:39 +00:00
Kconfig
kvm_mips.h
kvm.c	kvm: allow target-specific accelerator properties	2022-10-10 09:23:16 +02:00
meson.build
mips-defs.h	target/mips: introduce decodetree structure for Cavium Octeon extension	2022-07-12 22:30:09 +02:00
msa.c