qemu-e2k/target/arm
Peter Maydell 8196fe9d83 target/arm: Make Thumb store insns UNDEF for Rn==1111
The Arm ARM specifies that for Thumb encodings of the various plain
store insns, if the Rn field is 1111 then we must UNDEF.  This is
different from the Arm encodings, where this case is either
UNPREDICTABLE or has well-defined behaviour.  The exclusive stores,
store-release and STRD do not have this UNDEF case for any encoding.

Enforce the UNDEF for this case in the Thumb plain store insns.

Fixes: https://bugs.launchpad.net/qemu/+bug/1922887
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210408162402.5822-1-peter.maydell@linaro.org
2021-04-30 11:16:49 +01:00
..
a32-uncond.decode
a32.decode
arch_dump.c
arm_ldst.h
arm-powerctl.c
arm-powerctl.h
cpu64.c Revert "target/arm: Make number of counters in PMCR follow the CPU" 2021-04-06 11:49:14 +01:00
cpu_tcg.c Revert "target/arm: Make number of counters in PMCR follow the CPU" 2021-04-06 11:49:14 +01:00
cpu-param.h
cpu-qom.h
cpu.c target/arm: Make M-profile VTOR loads on reset handle memory aliasing 2021-03-23 11:47:31 +00:00
cpu.h Revert "target/arm: Make number of counters in PMCR follow the CPU" 2021-04-06 11:49:14 +01:00
crypto_helper.c
debug_helper.c
gdbstub64.c
gdbstub.c
helper-a64.c target/arm: Speed up aarch64 TBL/TBX 2021-03-05 15:17:34 +00:00
helper-a64.h target/arm: Speed up aarch64 TBL/TBX 2021-03-05 15:17:34 +00:00
helper-sve.h
helper.c Revert "target/arm: Make number of counters in PMCR follow the CPU" 2021-04-06 11:49:14 +01:00
helper.h
idau.h
internals.h target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe 2021-03-05 15:17:34 +00:00
iwmmxt_helper.c
kvm64.c Revert "target/arm: Make number of counters in PMCR follow the CPU" 2021-04-06 11:49:14 +01:00
kvm_arm.h hw/arm/virt: KVM: The IPA lower bound is 32 2021-03-12 12:47:11 +00:00
kvm-consts.h
kvm-stub.c
kvm.c hw/arm/virt: KVM: The IPA lower bound is 32 2021-03-12 12:47:11 +00:00
m_helper.c semihosting: Move include/hw/semihosting/ -> include/semihosting/ 2021-03-10 15:34:12 +00:00
m-nocp.decode
machine.c
meson.build
monitor.c
mte_helper.c target/arm: Check PAGE_WRITE_ORG for MTE writeability 2021-04-12 11:06:24 +01:00
neon_helper.c
neon-dp.decode
neon-ls.decode
neon-shared.decode
op_addsub.h
op_helper.c
pauth_helper.c
psci.c
sve_helper.c target/arm: Update sve reduction vs simd_desc 2021-03-12 12:40:10 +00:00
sve.decode
syndrome.h target/arm: Split out syndrome.h from internals.h 2021-02-16 13:16:18 +00:00
t16.decode
t32.decode
tlb_helper.c target/arm: Set ARMMMUFaultInfo.level in user-only arm_cpu_tlb_fill 2021-03-23 14:07:55 +00:00
trace-events
trace.h
translate-a64.c semihosting: Move include/hw/semihosting/ -> include/semihosting/ 2021-03-10 15:34:12 +00:00
translate-a64.h
translate-neon.c.inc
translate-sve.c target/arm: Update sve reduction vs simd_desc 2021-03-12 12:40:10 +00:00
translate-vfp.c.inc
translate.c target/arm: Make Thumb store insns UNDEF for Rn==1111 2021-04-30 11:16:49 +01:00
translate.h
vec_helper.c target/arm: Speed up aarch64 TBL/TBX 2021-03-05 15:17:34 +00:00
vec_internal.h
vfp_helper.c
vfp-uncond.decode
vfp.decode