qemu-e2k/hw/i386
Joao Martins 8504f12945 i386/pc: relocate 4g start to 1T where applicable
It is assumed that the whole GPA space is available to be DMA
addressable, within a given address space limit, except for a
tiny region before the 4G. Since Linux v5.4, VFIO validates
whether the selected GPA is indeed valid i.e. not reserved by
IOMMU on behalf of some specific devices or platform-defined
restrictions, and thus failing the ioctl(VFIO_DMA_MAP) with
 -EINVAL.

AMD systems with an IOMMU are examples of such platforms and
particularly may only have these ranges as allowed:

        0000000000000000 - 00000000fedfffff (0      .. 3.982G)
        00000000fef00000 - 000000fcffffffff (3.983G .. 1011.9G)
        0000010000000000 - ffffffffffffffff (1Tb    .. 16Pb[*])

We already account for the 4G hole, albeit if the guest is big
enough we will fail to allocate a guest with  >1010G due to the
~12G hole at the 1Tb boundary, reserved for HyperTransport (HT).

[*] there is another reserved region unrelated to HT that exists
in the 256T boundary in Fam 17h according to Errata #1286,
documeted also in "Open-Source Register Reference for AMD Family
17h Processors (PUB)"

When creating the region above 4G, take into account that on AMD
platforms the HyperTransport range is reserved and hence it
cannot be used either as GPAs. On those cases rather than
establishing the start of ram-above-4g to be 4G, relocate instead
to 1Tb. See AMD IOMMU spec, section 2.1.2 "IOMMU Logical
Topology", for more information on the underlying restriction of
IOVAs.

After accounting for the 1Tb hole on AMD hosts, mtree should
look like:

0000000000000000-000000007fffffff (prio 0, i/o):
         alias ram-below-4g @pc.ram 0000000000000000-000000007fffffff
0000010000000000-000001ff7fffffff (prio 0, i/o):
        alias ram-above-4g @pc.ram 0000000080000000-000000ffffffffff

If the relocation is done or the address space covers it, we
also add the the reserved HT e820 range as reserved.

Default phys-bits on Qemu is TCG_PHYS_ADDR_BITS (40) which is enough
to address 1Tb (0xff ffff ffff). On AMD platforms, if a
ram-above-4g relocation is attempted and the CPU wasn't configured
with a big enough phys-bits, an error message will be printed
due to the maxphysaddr vs maxusedaddr check previously added.

Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Joao Martins <joao.m.martins@oracle.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20220719170014.27028-11-joao.m.martins@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-07-26 10:40:58 -04:00
..
kvm i386/kvm: Replace abs64() with uabs64() from host-utils 2021-09-29 19:37:38 +10:00
xen hw/i386/xen/xen-hvm: Inline xen_piix_pci_write_config_client() and remove it 2022-06-29 00:24:59 +02:00
acpi-build.c hw/i386: add 4g boundary start to X86MachineState 2022-07-26 10:40:58 -04:00
acpi-build.h hw/acpi/ich9: Enable ACPI PCI hot-plug 2021-07-16 04:33:35 -04:00
acpi-common.c acpi: x86: madt: use build_append_int_noprefix() API to compose MADT table 2021-10-05 17:30:57 -04:00
acpi-common.h
acpi-microvm.c hw/acpi/microvm: turn on 8042 bit in FADT boot architecture flags if present 2022-03-07 17:43:14 -05:00
acpi-microvm.h
amd_iommu.c hw/i386/amd_iommu: Fix IOMMU event log encoding errors 2022-05-16 16:15:40 -04:00
amd_iommu.h
e820_memory_layout.c
e820_memory_layout.h Clean up header guards that don't match their file name 2022-05-11 16:49:06 +02:00
fw_cfg.c hw/i386/fw_cfg: Set SGX bits in feature control fw_cfg accordingly 2021-09-30 15:30:24 +02:00
fw_cfg.h
generic_event_device_x86.c
intel_iommu_internal.h intel-iommu: block output address in interrupt address range 2022-05-16 04:38:40 -04:00
intel_iommu.c intel-iommu: update iq_dw during post load 2022-05-16 04:38:40 -04:00
Kconfig hw/i386/pc: Allow instantiating a virtio-iommu device 2021-11-01 18:49:10 -04:00
kvmvapic.c
meson.build microvm: add device tree support. 2021-11-02 17:24:17 +01:00
microvm-dt.c hw/rtc/mc146818rtc: QOM'ify io_base offset 2022-06-11 11:44:50 +02:00
microvm-dt.h microvm: add device tree support. 2021-11-02 17:24:17 +01:00
microvm.c hw/i386: pass RNG seed via setup_data entry 2022-07-22 19:26:34 +02:00
multiboot.c target/i386: use DMA-enabled multiboot ROM for new-enough QEMU machine types 2021-11-02 15:57:27 +01:00
multiboot.h target/i386: use DMA-enabled multiboot ROM for new-enough QEMU machine types 2021-11-02 15:57:27 +01:00
pc_piix.c i386/pc: pass pci_hole64_size to pc_memory_init() 2022-07-26 10:40:58 -04:00
pc_q35.c i386/pc: pass pci_hole64_size to pc_memory_init() 2022-07-26 10:40:58 -04:00
pc_sysfw_ovmf-stubs.c
pc_sysfw_ovmf.c hw/i386: Replace magic number with field length calculation 2022-03-06 05:08:23 -05:00
pc_sysfw.c i386: factor out x86_firmware_configure() 2022-04-27 07:51:01 +02:00
pc.c i386/pc: relocate 4g start to 1T where applicable 2022-07-26 10:40:58 -04:00
port92.c
sgx-epc.c Mark remaining global TypeInfo instances as const 2022-02-21 13:30:20 +00:00
sgx-stub.c numa: Enable numa for SGX EPC sections 2021-12-10 09:47:18 +01:00
sgx.c hw/i386: add 4g boundary start to X86MachineState 2022-07-26 10:40:58 -04:00
trace-events hw: Fix misleading hexadecimal format 2022-03-24 10:38:42 +00:00
trace.h
vmmouse.c hw/i386/vmmouse: Require 'i8042' property to be set 2021-12-18 10:57:37 +01:00
vmport.c
x86-iommu-stub.c hw/i386/pc: Remove x86_iommu_get_type() 2021-11-01 18:49:10 -04:00
x86-iommu.c hw/i386/pc: Move IOMMU singleton into PCMachineState 2021-11-01 18:49:10 -04:00
x86.c hw/i386: add 4g boundary start to X86MachineState 2022-07-26 10:40:58 -04:00