Peter Maydell a3c1ca56c0 hw/char/pl011: Support all interrupt lines ... The PL011 UART has six interrupt lines: * RX (receive data) * TX (transmit data) * RT (receive timeout) * MS (modem status) * E (errors) * combined (logical OR of all the above) So far we have only emulated the combined interrupt line; add support for the others, so that boards that wire them up to different interrupt controller inputs can do so. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>		2019-02-21 18:17:46 +00:00
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bcm2835_aux.h
cadence_uart.h
cmsdk-apb-uart.h	hw/char/cmsdk-apb-uart.c: Implement CMSDK APB UART	2017-07-17 13:36:08 +01:00
digic-uart.h
escc.h	hw/char: remove legacy interface escc_init()	2018-02-16 12:14:26 +11:00
imx_serial.h	imx_serial: Generate interrupt on receive data ready if enabled	2018-08-20 11:24:31 +01:00
lm32_juart.h
nrf51_uart.h	arm: Add header to host common definition for nRF51 SOC peripherals	2019-01-07 15:23:47 +00:00
parallel.h	hw/isa: Move parallel_hds_isa_init() to hw/char/parallel-isa.c	2018-03-12 16:12:47 +01:00
pl011.h	hw/char/pl011: Support all interrupt lines	2019-02-21 18:17:46 +00:00
serial.h	hw/char/serial: Remove SerialState from "qemu/typedefs.h"	2019-01-22 05:14:33 +01:00
stm32f2xx_usart.h	hw/char/stm32f2xx_usart: fix TXE/TC bit handling	2018-02-22 15:12:51 +00:00
xilinx_uartlite.h