Peter Maydell 87a4b27034 target/arm: Handle VIRQ and VFIQ in arm_cpu_do_interrupt_aarch32() ... To run a VM in 32-bit EL1 our AArch32 interrupt handling code needs to be able to cope with VIRQ and VFIQ exceptions. These behave like IRQ and FIQ except that we don't need to try to route them to Monitor mode. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>		2017-01-20 11:15:07 +00:00
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alpha	cputlb: drop flush_global flag from tlb_flush	2017-01-13 14:24:37 +00:00
arm	target/arm: Handle VIRQ and VFIQ in arm_cpu_do_interrupt_aarch32()	2017-01-20 11:15:07 +00:00
cris	qom/cpu: move tlb_flush to cpu_common_reset	2017-01-13 14:24:31 +00:00
i386	This is the same as the v3 posted except a re-base and a few extra signoffs	2017-01-16 18:23:02 +00:00
lm32	qom/cpu: move tlb_flush to cpu_common_reset	2017-01-13 14:24:31 +00:00
m68k	This is the same as the v3 posted except a re-base and a few extra signoffs	2017-01-16 18:23:02 +00:00
microblaze	cputlb: drop flush_global flag from tlb_flush	2017-01-13 14:24:37 +00:00
mips	cputlb: drop flush_global flag from tlb_flush	2017-01-13 14:24:37 +00:00
moxie	qom/cpu: move tlb_flush to cpu_common_reset	2017-01-13 14:24:31 +00:00
openrisc	cputlb: drop flush_global flag from tlb_flush	2017-01-13 14:24:37 +00:00
ppc	This is the same as the v3 posted except a re-base and a few extra signoffs	2017-01-16 18:23:02 +00:00
s390x	This is the same as the v3 posted except a re-base and a few extra signoffs	2017-01-16 18:23:02 +00:00
sh4	cputlb: drop flush_global flag from tlb_flush	2017-01-13 14:24:37 +00:00
sparc	target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs	2017-01-18 22:03:44 +01:00
tilegx	qom/cpu: move tlb_flush to cpu_common_reset	2017-01-13 14:24:31 +00:00
tricore	qom/cpu: move tlb_flush to cpu_common_reset	2017-01-13 14:24:31 +00:00
unicore32	cputlb: drop flush_global flag from tlb_flush	2017-01-13 14:24:37 +00:00
xtensa	cputlb: drop flush_global flag from tlb_flush	2017-01-13 14:24:37 +00:00