Peter Maydell 87a4b27034 target/arm: Handle VIRQ and VFIQ in arm_cpu_do_interrupt_aarch32() ... To run a VM in 32-bit EL1 our AArch32 interrupt handling code needs to be able to cope with VIRQ and VFIQ exceptions. These behave like IRQ and FIQ except that we don't need to try to route them to Monitor mode. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>		2017-01-20 11:15:07 +00:00
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arch_dump.c
arm_ldst.h
arm-powerctl.c
arm-powerctl.h
arm-semi.c
cpu64.c
cpu-qom.h
cpu.c	qom/cpu: move tlb_flush to cpu_common_reset	2017-01-13 14:24:31 +00:00
cpu.h	qom/cpu: move tlb_flush to cpu_common_reset	2017-01-13 14:24:31 +00:00
crypto_helper.c
gdbstub64.c
gdbstub.c
helper-a64.c	target-arm: Use clrsb helper	2017-01-10 08:47:48 -08:00
helper-a64.h	target-arm: Use clrsb helper	2017-01-10 08:47:48 -08:00
helper.c	target/arm: Handle VIRQ and VFIQ in arm_cpu_do_interrupt_aarch32()	2017-01-20 11:15:07 +00:00
helper.h	target-arm: Use clz opcode	2017-01-10 08:06:11 -08:00
internals.h
iwmmxt_helper.c
kvm32.c
kvm64.c
kvm_arm.h
kvm-consts.h
kvm-stub.c
kvm.c
machine.c
Makefile.objs
monitor.c
neon_helper.c
op_addsub.h
op_helper.c	target-arm: Log AArch64 exception returns	2016-12-27 14:59:25 +00:00
psci.c
trace-events
translate-a64.c	target/arm: Fix ubfx et al for aarch64	2017-01-13 09:48:20 -08:00
translate.c	target-arm: Use clz opcode	2017-01-10 08:06:11 -08:00
translate.h