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qemu-e2k/target/riscv
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Yifei Jiang 33a9a57d2c target/riscv: raise exception to HS-mode at get_physical_address 
VS-stage translation at get_physical_address needs to translate pte
address by G-stage translation. But the G-stage translation error
can not be distinguished from VS-stage translation error in
riscv_cpu_tlb_fill. On migration, destination needs to rebuild pte,
and this G-stage translation error must be handled by HS-mode. So
introduce TRANSLATE_STAGE2_FAIL so that riscv_cpu_tlb_fill could
distinguish and raise it to HS-mode.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201014101728.848-1-jiangyifei@huawei.com
[ Change by AF:
 - Clarify the fault_pte_addr shift
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 		2020-10-22 12:00:22 -07:00
..
insn_trans target/riscv: Support the Virtual Instruction fault 2020-08-25 09:11:36 -07:00
cpu-param.h tcg: Split out target/arch/cpu-param.h 2019-06-10 07:03:34 -07:00
cpu.c target/riscv: Set instance_align on RISCVCPU TypeInfo 2020-09-18 13:59:51 -04:00
cpu.h target/riscv: raise exception to HS-mode at get_physical_address 2020-10-22 12:00:22 -07:00
cpu_bits.h target/riscv: Support the Virtual Instruction fault 2020-08-25 09:11:36 -07:00
cpu_helper.c target/riscv: raise exception to HS-mode at get_physical_address 2020-10-22 12:00:22 -07:00
cpu_user.h Supply missing header guards 2019-06-12 13:20:21 +02:00
csr.c icount: rename functions to be consistent with the module name 2020-10-05 16:41:22 +02:00
fpu_helper.c target/riscv: Check nanboxed inputs to fp helpers 2020-08-21 22:37:55 -07:00
gdbstub.c gdbstub: extend GByteArray to read register helpers 2020-03-17 17:38:38 +00:00
helper.h target/riscv: Support the Virtual Instruction fault 2020-08-25 09:11:36 -07:00
insn16-32.decode target/riscv: Split RVC32 and RVC64 insns into separate files 2019-05-24 12:09:22 -07:00
insn16-64.decode target/riscv: Add checks for several RVC reserved operands 2019-05-24 12:09:25 -07:00
insn16.decode target/riscv: Add checks for several RVC reserved operands 2019-05-24 12:09:25 -07:00
insn32-64.decode target/riscv: Allow generating hlv/hlvx/hsv instructions 2020-08-25 09:11:35 -07:00
insn32.decode target/riscv: Allow generating hlv/hlvx/hsv instructions 2020-08-25 09:11:35 -07:00
instmap.h target/riscv: progressively load the instruction during decode 2020-02-25 20:20:23 +00:00
internals.h target/riscv: Check nanboxed inputs to fp helpers 2020-08-21 22:37:55 -07:00
meson.build meson: target 2020-08-21 06:30:35 -04:00
monitor.c target/riscv: Drop support for ISA spec version 1.09.1 2020-06-03 09:11:51 -07:00
op_helper.c target/riscv: Fix implementation of HLVX.WU instruction 2020-10-22 12:00:22 -07:00
pmp.c target/riscv: Change the TLB page size depends on PMP entries. 2020-08-21 22:37:55 -07:00
pmp.h target/riscv: Change the TLB page size depends on PMP entries. 2020-08-21 22:37:55 -07:00
trace-events trace-events: Fix attribution of trace points to source 2020-09-09 17:17:58 +01:00
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
translate.c target/riscv: Update the Hypervisor trap return/entry 2020-08-25 09:11:36 -07:00
vector_helper.c softfloat: Implement the full set of comparisons for float16 2020-08-28 10:48:07 -07:00