qemu-e2k/target/riscv
Peter Maydell 441e0eefab Error reporting patches for 2024-03-12
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Merge tag 'pull-error-2024-03-12' of https://repo.or.cz/qemu/armbru into staging

Error reporting patches for 2024-03-12

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# gpg: Signature made Tue 12 Mar 2024 13:30:14 GMT
# gpg:                using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653
# gpg:                issuer "armbru@redhat.com"
# gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full]
# gpg:                 aka "Markus Armbruster <armbru@pond.sub.org>" [full]
# Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867  4E5F 3870 B400 EB91 8653

* tag 'pull-error-2024-03-12' of https://repo.or.cz/qemu/armbru:
  target/loongarch: Fix query-cpu-model-expansion to reject props
  target: Improve error reporting for CpuModelInfo member @props
  target/i386: Fix query-cpu-model-expansion to reject props
  target: Simplify type checks for CpuModelInfo member @props

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-03-12 16:55:56 +00:00
..
insn_trans trans_rvv.c.inc: remove 'is_store' bool from load/store fns 2024-03-08 20:48:03 +10:00
kvm migration: export migration_is_running 2024-03-11 16:28:59 -04:00
tcg target/riscv: Promote svade to a normal extension 2024-03-08 16:35:28 +10:00
arch_dump.c
bitmanip_helper.c
common-semi-target.h
cpu_bits.h target/riscv: FCSR doesn't contain vxrm and vxsat 2024-02-09 20:43:14 +10:00
cpu_cfg.h RISC-V: Add support for Ztso 2024-03-08 19:47:48 +10:00
cpu_helper.c target/riscv: Fix privilege mode of G-stage translation for debugging 2024-03-08 20:48:03 +10:00
cpu_user.h
cpu_vendorid.h
cpu-param.h
cpu-qom.h target/riscv: add rv32i, rv32e and rv64e CPUs 2024-02-09 20:49:41 +10:00
cpu.c target: Replace CPU_GET_CLASS(cpu -> obj) in cpu_reset_hold() handler 2024-03-12 11:46:16 +01:00
cpu.h target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit 2024-03-08 20:48:03 +10:00
crypto_helper.c
csr.c target/riscv: UPDATE xATP write CSR 2024-03-08 16:38:09 +10:00
debug.c target/riscv: Implement optional CSR mcontext of debug Sdtrig extension 2024-02-09 20:40:32 +10:00
debug.h
fpu_helper.c
gdbstub.c gdbstub: Add members to identify registers to GDBFeature 2024-02-28 09:10:11 +00:00
helper.h
insn16.decode
insn32.decode
instmap.h
internals.h
Kconfig kconfig: use "select" to enable semihosting 2024-02-09 17:52:30 +00:00
m128_helper.c
machine.c target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit 2024-03-08 20:48:03 +10:00
meson.build
monitor.c
op_helper.c target/riscv: Replace cpu_mmu_index with riscv_env_mmu_index 2024-02-03 16:46:10 +10:00
pmp.c target/riscv: pmp: Ignore writes when RW=01 and MML=0 2024-01-10 18:47:47 +10:00
pmp.h
pmu.c
pmu.h target/riscv: Add missing include guard in pmu.h 2024-03-08 16:39:32 +10:00
riscv-qmp-cmds.c target: Improve error reporting for CpuModelInfo member @props 2024-03-12 14:03:00 +01:00
sbi_ecall_interface.h
time_helper.c
time_helper.h
trace-events
trace.h
translate.c RISC-V: Add support for Ztso 2024-03-08 19:47:48 +10:00
vcrypto_helper.c
vector_helper.c target/riscv: Fix shift count overflow 2024-03-08 20:48:03 +10:00
vector_internals.c riscv: Clean up includes 2024-01-30 21:20:20 +03:00
vector_internals.h riscv: Clean up includes 2024-01-30 21:20:20 +03:00
xthead.decode
XVentanaCondOps.decode
zce_helper.c