Dayeol Lee 9667e53573

target/riscv: PMP violation due to wrong size parameter ...

riscv_cpu_tlb_fill() uses the `size` parameter to check PMP violation
using pmp_hart_has_privs().
However, if the size is unknown (=0), the ending address will be
`addr - 1` as it is `addr + size - 1` in `pmp_hart_has_privs()`.
This always causes a false PMP violation on the starting address of the
range, as `addr - 1` is not in the range.

In order to fix, we just assume that all bytes from addr to the end of
the page will be accessed if the size is unknown.

Signed-off-by: Dayeol Lee <dayeol@berkeley.edu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

2019-10-28 08:46:33 -07:00

..

insn_trans

tcg: TCGMemOp is now accelerator independent MemOp

2019-09-03 08:30:38 -07:00

cpu_bits.h

target/riscv: Update the Hypervisor CSRs to v0.4

2019-09-17 08:42:43 -07:00

cpu_helper.c

linux-user/riscv: Propagate fault address

2019-10-28 07:47:27 -07:00

cpu_user.h

Supply missing header guards

2019-06-12 13:20:21 +02:00

cpu-param.h

tcg: Split out target/arch/cpu-param.h

2019-06-10 07:03:34 -07:00

cpu.c

RISC-V: Implement cpu_do_transaction_failed

2019-10-28 07:47:27 -07:00

cpu.h

RISC-V: Implement cpu_do_transaction_failed

2019-10-28 07:47:27 -07:00

csr.c

riscv: Skip checking CSR privilege level in debugger mode

2019-10-28 07:46:53 -07:00

fpu_helper.c

target/riscv: rationalise softfloat includes

2019-08-19 12:07:13 +01:00

gdbstub.c

target/riscv: Make the priv register writable by GDB

2019-10-28 07:47:29 -07:00

helper.h

RISC-V CPU Helpers

2018-03-07 08:30:28 +13:00

insn16-32.decode

target/riscv: Split RVC32 and RVC64 insns into separate files

2019-05-24 12:09:22 -07:00

insn16-64.decode

target/riscv: Add checks for several RVC reserved operands

2019-05-24 12:09:25 -07:00

insn16.decode

target/riscv: Add checks for several RVC reserved operands

2019-05-24 12:09:25 -07:00

insn32-64.decode

target/riscv: Convert RV64D insns to decodetree

2019-03-13 10:34:06 +01:00

insn32.decode

target/riscv: Name the argument sets for all of insn32 formats

2019-05-24 12:09:22 -07:00

instmap.h

Supply missing header guards

2019-06-12 13:20:21 +02:00

Makefile.objs

riscv: hmp: Add a command to show virtual memory mappings

2019-09-17 08:42:43 -07:00

monitor.c

riscv: hmp: Add a command to show virtual memory mappings

2019-09-17 08:42:43 -07:00

op_helper.c

target/riscv: Use env_cpu, env_archcpu

2019-06-10 07:03:42 -07:00

pmp.c

target/riscv: PMP violation due to wrong size parameter

2019-10-28 08:46:33 -07:00

pmp.h

RISC-V: Check for the effective memory privilege mode during PMP checks

2019-06-23 23:44:41 -07:00

trace-events

target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events

2019-09-17 08:42:42 -07:00

translate.c

target/riscv: Remove redundant declaration pragmas

2019-08-19 08:13:14 -07:00