qemu-e2k/target
Daniel Henrique Barboza 136cb9cc03 target/riscv/kvm.c: fix mvendorid size in vcpu_set_machine_ids()
cpu->cfg.mvendorid is a 32 bit field and kvm_set_one_reg() always write
a target_ulong val, i.e. a 64 bit field in a 64 bit host.

Given that we're passing a pointer to the mvendorid field, the reg is
reading 64 bits starting from mvendorid and going 32 bits in the next
field, marchid. Here's an example:

$ ./qemu-system-riscv64 -machine virt,accel=kvm -m 2G -smp 1 \
   -cpu rv64,marchid=0xab,mvendorid=0xcd,mimpid=0xef(...)

(inside the guest)
 # cat /proc/cpuinfo
processor	: 0
hart		: 0
isa		: rv64imafdc_zicbom_zicboz_zihintpause_zbb_sstc
mmu		: sv57
mvendorid	: 0xab000000cd
marchid		: 0xab
mimpid		: 0xef

'mvendorid' was written as a combination of 0xab (the value from the
adjacent field, marchid) and its intended value 0xcd.

Fix it by assigning cpu->cfg.mvendorid to a target_ulong var 'reg' and
use it as input for kvm_set_one_reg(). Here's the result with this patch
applied and using the same QEMU command line:

 # cat /proc/cpuinfo
processor	: 0
hart		: 0
isa		: rv64imafdc_zicbom_zicboz_zihintpause_zbb_sstc
mmu		: sv57
mvendorid	: 0xcd
marchid		: 0xab
mimpid		: 0xef

This bug affects only the generic (rv64) CPUs when running with KVM in a
64 bit env since the 'host' CPU does not allow the machine IDs to be
changed via command line.

Fixes: 1fb5a622f7 ("target/riscv: handle mvendorid/marchid/mimpid for KVM CPUs")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230802180058.281385-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-08-11 14:16:26 -04:00
..
alpha other architectures: spelling fixes 2023-07-25 17:14:07 +03:00
arm target/arm/tcg: Don't build AArch64 decodetree files for qemu-system-arm 2023-07-31 11:41:21 +01:00
avr target/avr: Fix handling of interrupts above 33. 2023-07-08 07:24:38 +03:00
cris other architectures: spelling fixes 2023-07-25 17:14:07 +03:00
hexagon target: Widen pc/cs_base in cpu_get_tb_cpu_state 2023-06-26 17:32:59 +02:00
hppa target/hppa: Move iaoq registers and thus reduce generated code size 2023-08-04 00:02:56 +02:00
i386 target/i386: Check CR0.TS before enter_mmx 2023-08-04 11:42:18 +02:00
loongarch other architectures: spelling fixes 2023-07-25 17:14:07 +03:00
m68k target/m68k: Fix semihost lseek offset computation 2023-08-01 23:52:23 +02:00
microblaze other architectures: spelling fixes 2023-07-25 17:14:07 +03:00
mips target/mips: Avoid shift by negative number in page_table_walk_refill() 2023-07-25 14:41:16 +02:00
nios2 target/nios2: Fix semihost lseek offset computation 2023-08-01 23:52:23 +02:00
openrisc target/openrisc: Set EPCR to next PC on FPE exceptions 2023-07-31 22:01:03 +01:00
ppc target/ppc: Fix VRMA page size for ISA v3.0 2023-08-04 12:22:03 -03:00
riscv target/riscv/kvm.c: fix mvendorid size in vcpu_set_machine_ids() 2023-08-11 14:16:26 -04:00
rx other architectures: spelling fixes 2023-07-25 17:14:07 +03:00
s390x target/s390x: Move trans_exc_code update to do_program_interrupt 2023-07-31 12:19:13 -07:00
sh4 target: Widen pc/cs_base in cpu_get_tb_cpu_state 2023-06-26 17:32:59 +02:00
sparc trivial-patches 25-07-2023 2023-07-25 16:30:52 +01:00
tricore target/tricore: Rename tricore_feature 2023-07-25 17:18:51 +03:00
xtensa target/xtensa: Assert that interrupt level is within bounds 2023-07-06 13:26:43 +01:00
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target/loongarch: Add target build suport 2022-06-06 18:09:03 +00:00