Thomas Huth 35c7f5254b target/riscv/vector_helper: Fix build on 32-bit big endian hosts ... The code currently fails to compile on 32-bit big endian hosts: target/riscv/vector_helper.c: In function 'vext_clear': target/riscv/vector_helper.c:154:16: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast] memset((void *)((uintptr_t)tail & ~(7ULL)), 0, part1); ^ target/riscv/vector_helper.c:155:16: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast] memset((void *)(((uintptr_t)tail + 8) & ~(7ULL)), 0, part2); ^ cc1: all warnings being treated as errors We should not use "long long" (i.e. 64-bit) values here to avoid the problem. Switch to our QEMU_ALIGN_PTR_DOWN/UP macros instead. Fixes: 751538d5da ("add vector stride load and store instructions") Suggested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20200804170055.2851-3-thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>		2020-08-05 10:43:45 +02:00
..
insn_trans	target/riscv: fix vector index load/store constraints	2020-07-22 09:39:46 -07:00
cpu_bits.h	target/riscv: support vector extension csr	2020-07-02 09:19:32 -07:00
cpu_helper.c
cpu_user.h
cpu-param.h
cpu.c	target/riscv: configure and turn on vector extension from command line	2020-07-02 09:19:34 -07:00
cpu.h	target/riscv: fix vill bit index in vtype register	2020-07-13 17:25:37 -07:00
csr.c	target/riscv: Fix the range of pmpcfg of CSR funcion table	2020-07-22 09:41:36 -07:00
fpu_helper.c	target/riscv: vector floating-point classify instructions	2020-07-02 09:19:33 -07:00
gdbstub.c
helper.h	target/riscv: vector compress instruction	2020-07-02 09:19:34 -07:00
insn16-32.decode
insn16-64.decode
insn16.decode
insn32-64.decode	target/riscv: add vector amo operations	2020-07-02 09:19:33 -07:00
insn32.decode	target/riscv: vector compress instruction	2020-07-02 09:19:34 -07:00
instmap.h
internals.h	target/riscv: integer scalar move instruction	2020-07-02 09:19:33 -07:00
Makefile.objs	target/riscv: add vector configure instruction	2020-07-02 09:19:32 -07:00
monitor.c
op_helper.c	target/riscv: Implement checks for hfence	2020-06-19 08:24:07 -07:00
pmp.c	target/riscv: Fix pmp NA4 implementation	2020-07-13 17:25:37 -07:00
pmp.h
trace-events
translate.c	target/riscv: add vector stride load and store instructions	2020-07-02 09:19:32 -07:00
vector_helper.c	target/riscv/vector_helper: Fix build on 32-bit big endian hosts	2020-08-05 10:43:45 +02:00