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qemu-e2k/target/riscv/insn_trans
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eopXD 02b511985e target/riscv: rvv: Fix early exit condition for whole register load/store 
Vector whole register load instructions have EEW encoded in the opcode,
so we shouldn't take SEW here. Vector whole register store instructions
are always EEW=8.

Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165181414065.18540.14828125053334599921-0@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 		2022-05-24 09:48:20 +10:00
..
trans_privileged.c.inc target/riscv: Sign extend pc for different XLEN 2022-01-21 15:52:57 +10:00
trans_rva.c.inc target/riscv: Calculate address according to XLEN 2022-01-21 15:52:57 +10:00
trans_rvb.c.inc target/riscv: rvk: add support for zbkx extension 2022-04-29 10:47:45 +10:00
trans_rvd.c.inc target/riscv: add support for zdinx 2022-03-03 13:14:50 +10:00
trans_rvf.c.inc target/riscv: add support for zfinx 2022-03-03 13:14:50 +10:00
trans_rvh.c.inc exec/memop: Adding signedness to quad definitions 2022-01-08 15:46:10 +10:00
trans_rvi.c.inc target/riscv: access configuration through cfg_ptr in DisasContext 2022-02-16 12:24:18 +10:00
trans_rvk.c.inc target/riscv: rvk: add support for zksed/zksh extension 2022-04-29 10:47:45 +10:00
trans_rvm.c.inc target/riscv: support for 128-bit M extension 2022-01-08 15:46:10 +10:00
trans_rvv.c.inc target/riscv: rvv: Fix early exit condition for whole register load/store 2022-05-24 09:48:20 +10:00
trans_rvzfh.c.inc target/riscv: add support for zhinx/zhinxmin 2022-03-03 13:14:50 +10:00
trans_svinval.c.inc target/riscv: add support for svinval extension 2022-02-16 12:25:52 +10:00
trans_xventanacondops.c.inc target/riscv: Add XVentanaCondOps custom extension 2022-02-16 12:24:18 +10:00