Peter Maydell 956d272eb2 target-arm: A64: Add logic ops from SIMD 3 same group ... Add support for the logical operations (ORR, AND, BIC, ORN, EOR, BSL, BIT and BIF) from the SIMD 3 register same group (C3.6.16). Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>		2014-01-31 14:47:37 +00:00
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arm-semi.c
cpu64.c
cpu-qom.h
cpu.c	ARM: Convert MIDR to a property	2014-01-31 14:47:32 +00:00
cpu.h	target-arm: Move arm_rmode_to_sf to a shared location.	2014-01-31 14:47:33 +00:00
crypto_helper.c
gdbstub64.c
gdbstub.c
helper-a64.c
helper-a64.h
helper.c	target-arm: Add set_neon_rmode helper	2014-01-31 14:47:35 +00:00
helper.h	target-arm: Add set_neon_rmode helper	2014-01-31 14:47:35 +00:00
iwmmxt_helper.c
kvm32.c
kvm64.c
kvm_arm.h
kvm-consts.h
kvm-stub.c
kvm.c
machine.c
Makefile.objs
neon_helper.c
op_addsub.h
op_helper.c
translate-a64.c	target-arm: A64: Add logic ops from SIMD 3 same group	2014-01-31 14:47:37 +00:00
translate.c	target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTM	2014-01-31 14:47:35 +00:00
translate.h