f72dbf3d26
The receive fifo full bit should be set when 1 character is received and the fifo is disabled or when 16 characters are in the fifo. Signed-off-by: Rob Herring <rob.herring@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1395166721-15716-4-git-send-email-robherring2@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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cadence_uart.c | ||
debugcon.c | ||
digic-uart.c | ||
escc.c | ||
etraxfs_ser.c | ||
exynos4210_uart.c | ||
grlib_apbuart.c | ||
imx_serial.c | ||
ipoctal232.c | ||
lm32_juart.c | ||
lm32_uart.c | ||
Makefile.objs | ||
mcf_uart.c | ||
milkymist-uart.c | ||
omap_uart.c | ||
parallel.c | ||
pl011.c | ||
sclpconsole-lm.c | ||
sclpconsole.c | ||
serial-isa.c | ||
serial-pci.c | ||
serial.c | ||
sh_serial.c | ||
spapr_vty.c | ||
virtio-console.c | ||
virtio-serial-bus.c | ||
xen_console.c | ||
xilinx_uartlite.c |